add provided RTL models
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Arthur Lu
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55
RTL/ALU.sv
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55
RTL/ALU.sv
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// Create Date: 2018.10.15
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// Module Name: ALU
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// Project Name: CSE141L
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//
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// Revision 2022.04.30
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// Additional Comments:
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// combinational (unclocked) ALU
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import definitions::*; // includes package "definitions"
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module ALU #(parameter W=8)(
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input [W-1:0] InputA, // data inputs
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InputB,
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input SC_in, // shift or carry in
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input [ 2:0] OP, // ALU opcode, part of microcode
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output logic [W-1:0] Out, // or: output reg [7:0] OUT,
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output logic PF, // reduction parity
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output logic Zero, // output = zero flag
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output logic SC_out // shift or carry out
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// you may provide additional status flags as inputs, if desired
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);
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op_mne op_mnemonic; // type enum: used for convenient waveform viewing
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// InputA = current LFSR state
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// InputB = tap_pattern
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always_comb begin
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Out = 0;
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SC_out = 0; // No Op = default
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case(OP)
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kADD : {SC_out,Out} = {1'b0,InputA} + InputB; // add
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kLSH : {SC_out,Out} = {InputA[7:0],SC_in}; // shift left, fill in with SC_in
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// for logical left shift, tie SC_in = 0
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kRSH : {Out,SC_out} = {SC_in, InputA[7:0]}; // shift right
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kXOR : Out = InputA ^ InputB; // exclusive OR
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kAND : Out = InputA & InputB; // bitwise AND
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endcase
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end
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always_comb // assign Zero = !Out;
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case(Out)
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'b0 : Zero = 1'b1;
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default : Zero = 1'b0;
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endcase
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always_comb
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PF = ^Out; // Out[7]^Out[6]^...^Out[0] // reduction XOR
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always_comb
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op_mnemonic = op_mne'(OP); // displays operation name in waveform viewer
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endmodule
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/* InputA=10101010 SC_in = 1
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kLSH Out = 01010101
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*/
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56
RTL/Ctrl.sv
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56
RTL/Ctrl.sv
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@ -0,0 +1,56 @@
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// CSE141L
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import definitions::*;
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// control decoder (combinational, not clocked)
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// inputs from instrROM, ALU flags
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// outputs to program_counter (fetch unit)
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module Ctrl (
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input[ 8:0] Instruction, // machine code
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input[ 7:0] DatMemAddr,
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output logic Jump ,
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BranchEn ,
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RegWrEn , // write to reg_file (common)
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MemWrEn , // write to mem (store only)
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LoadInst , // mem or ALU to reg_file ?
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PCTarg ,
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tapSel ,
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Ack // "done w/ program"
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// output logic[2:0] ALU_inst
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);
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/* ***** All numerical values are completely arbitrary and for illustration only *****
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*/
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// ALU commands
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//assign ALU_inst = Instruction[2:0];
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// STR commands only -- write to data_memory
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assign MemWrEn = Instruction[8:6]==3'b110;
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// all but STR and NOOP (or maybe CMP or TST) -- write to reg_file
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assign RegWrEn = Instruction[8:7]!=2'b11;
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// route data memory --> reg_file for loads
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// whenever instruction = 9'b110??????;
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assign LoadInst = Instruction[8:6]==3'b110; // calls out load specially
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assign tapSel = LoadInst && DatMemAddr=='d62;
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// jump enable command to program counter / instruction fetch module on right shift command
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// equiv to simply: assign Jump = Instruction[2:0] == kRSH;
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always_comb
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if(Instruction[2:0] == kRSH)
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Jump = 1;
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else
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Jump = 0;
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// branch every time instruction = 9'b?????1111;
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assign BranchEn = &Instruction[3:0];
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// whenever branch or jump is taken, PC gets updated or incremented from "Target"
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// PCTarg = 2-bit address pointer into Target LUT (PCTarg in --> Target out
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assign PCTarg = Instruction[3:2];
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// reserve instruction = 9'b111111111; for Ack
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assign Ack = &Instruction;
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endmodule
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39
RTL/DataMem.sv
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39
RTL/DataMem.sv
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// Create Date: 2017.01.25
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// Revision: 2022.05.04 made data width parametric
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// Design Name:
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// Module Name: DataMem
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// single address pointer for both read and write
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// CSE141L
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module DataMem #(parameter W=8, D=8)(
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input Clk,
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Reset, // again, note use of Reset for preloads
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WriteEn,
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input [D-1:0] DataAddress, // 8-bit-wide pointer to 256-deep memory
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input [W-1:0] DataIn, // 8-bit-wide data path, also
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output logic[W-1:0] DataOut);
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logic [W-1:0] Core[2**D]; // 8x256 two-dimensional array -- the memory itself
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always_comb // reads are combinational
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DataOut = Core[DataAddress];
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/* optional way to plant constants into DataMem at startup
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initial
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$readmemh("dataram_init.list", Core);
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*/
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always_ff @ (posedge Clk) // writes are sequential
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/*( Reset response is needed only for initialization (see inital $readmemh above for another choice)
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if you do not need to preload your data memory with any constants, you may omit the if(Reset) and the else,
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and go straight to if(WriteEn) ...
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*/
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if(Reset) begin
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// you may initialize your memory w/ constants, if you wish
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for(int i=128;i<256;i++)
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Core[ i] <= 0;
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Core[ 16] <= 254; // overrides the 0 ***sample only***
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Core[244] <= 5; // likewise
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end
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else if(WriteEn)
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Core[DataAddress] <= DataIn;
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endmodule
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24
RTL/Definitions.sv
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24
RTL/Definitions.sv
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//This file defines the parameters used in the alu
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// CSE141L
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// Rev. 2020.5.27
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// import package into each module that needs it
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// packages very useful for declaring global variables
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package definitions;
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/* Instruction map
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const logic [2:0]kADD = 3'b000;
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const logic [2:0]kLSH = 3'b001;
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const logic [2:0]kRSH = 3'b010;
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const logic [2:0]kXOR = 3'b011;
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const logic [2:0]kAND = 3'b100;
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const logic [2:0]kSUB = 3'b101;
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const logic [2:0]kCLR = 3'b110;
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*/
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// enum names will appear in timing diagram
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typedef enum logic[2:0] {
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ADD, LSH, BSH, XOR,
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AND, SUB, CLR } op_mne;
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// note: kADD is of type logic[2:0] (3-bit binary)
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// ADD is of type enum -- equiv., but watch casting
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// see ALU.sv for how to handle this
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endpackage // definitions
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36
RTL/InstFetch.sv
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36
RTL/InstFetch.sv
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// Design Name: basic_proc
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// Module Name: InstFetch
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// Project Name: CSE141L
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// Description: instruction fetch (pgm ctr) for processor
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//
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// Revision: 2019.01.27
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// Suggested ProgCtr width 10 t0 12 bits
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module InstFetch #(parameter T=10)( // PC width -- up to 32, if you like
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input Reset, // reset, init, etc. -- force PC to 0
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Start, // begin next program in series (request issued by test bench)
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Clk, // PC can change on pos. edges only
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BranchAbs, // jump unconditionally to Target value
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BranchRelEn, // jump conditionally to Target + PC
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ALU_flag, // flag from ALU, e.g. Zero, Carry, Overflow, Negative (from ARM)
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input [T-1:0] Target, // jump ... "how high?"
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output logic [T-1:0] ProgCtr // the program counter register itself
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);
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// you may wish to use either absolute or relative branching
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// you may use both, but you will need appropriate control bits
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// branch/jump is how we handle gosub and return to main
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// program counter can clear to 0, increment, or jump
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always_ff @(posedge Clk) // or just always; always_ff is a linting construct
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if(Reset)
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ProgCtr <= 0; // for first program; want different value for 2nd or 3rd
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else if(Start) // hold while start asserted; commence when released
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ProgCtr <= 0; //or <= ProgCtr; holds at starting value
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else if(BranchAbs) // unconditional absolute jump
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ProgCtr <= Target; // how would you make it conditional and/or relative?
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else if(BranchRelEn && ALU_flag) // conditional relative jump
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ProgCtr <= Target + ProgCtr; // how would you make it unconditional and/or absolute
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else
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ProgCtr <= ProgCtr+'b1; // default increment (no need for ARM/MIPS +4 -- why?)
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endmodule
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32
RTL/InstFetch_TB.sv
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32
RTL/InstFetch_TB.sv
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module InstFetch_TB();
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logic Reset = 1'b1,
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Start = 1'b0,
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Clk = 1'b0,
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BranchAbs = 1'b0,
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BranchRelEn = 1'b0,
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ALU_flag = 1'b0;
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logic [9:0] Target = 'b1; //10'h3fc;//'1; -4
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wire [9:0] ProgCtr;
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InstFetch IF1(.*);
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always begin
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#5ns Clk = 1'b1;
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#5ns Clk = 1'b0;
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end
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initial begin
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#20ns Reset = 1'b0;
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#20ns Start = 1'b1;
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#20ns Start = 1'b0;
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#120ns BranchAbs = 1'b1; // should reset PC to 0
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#30ns BranchAbs = 1'b0;
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#250ns BranchRelEn = 1'b1;
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Target = 'h3fc; // -4
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#20ns ALU_flag = 1'b1;
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#40ns ALU_flag = 1'b0;
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#240ns $stop;
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end
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endmodule
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52
RTL/InstROM.sv
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52
RTL/InstROM.sv
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// Create Date: 15:50:22 10/02/2019
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// Design Name:
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// Module Name: InstROM
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// Project Name: CSE141L
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// Tool versions:
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// Description: Verilog module -- instruction ROM template
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// preprogrammed with instruction values (see case statement)
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//
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// Revision: 2020.08.08
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//
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module InstROM #(parameter A=12, W=9) (
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input [A-1:0] InstAddress,
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output logic[W-1:0] InstOut);
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// (usually recommended) expression
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// need $readmemh or $readmemb to initialize all of the elements
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// declare 2-dimensional array, W bits wide, 2**A words deep
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logic[W-1:0] inst_rom[2**A];
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always_comb InstOut = inst_rom[InstAddress];
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initial begin // load from external text file
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$readmemb("machine_code.txt",inst_rom);
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end
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// Sample instruction format:
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// {3bit opcode, 3bit rs or rt, 3bit rt, immediate, or branch target}
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// then use LUT to map 3 bits to 10 for branch target, 8 for immediate
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/* alternative to code shown below, which may be simpler -- either is fine
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always_comb begin
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InstOut = 'b0000000000; // default
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case (InstAddress)
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//opcode = 0 lhw, rs = 0, rt = 1
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0 : InstOut = 'b0000000001; // load from address at reg 0 to reg 1
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// opcode = 1 addi, rs/rt = 1, immediate = 1
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1 : InstOut = 'b0001001001; // addi reg 1 and 1
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// opcode = 2 shw, rs = 0, rt = 1
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2 : InstOut = 'b0010000001; // sw reg 1 to address in reg 0
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// opcode = 3 beqz, rs = 1, target = 1
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3 : InstOut = 'b0011001001; // beqz reg1 to absolute address 1
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// opcode = 15 halt
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4 : InstOut = '1; // equiv to 10'b1111111111 or 'b1111111111 halt
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// (default case already covered by opening statement)
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endcase
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end
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*/
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endmodule
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46
RTL/RegFile.sv
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46
RTL/RegFile.sv
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// Create Date: 2019.01.25
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// Design Name: CSE141L
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// Module Name: reg_file
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// Revision: 2022.05.04
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// Additional Comments: allows preloading with user constants
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// This version is fully synthesizable and highly recommended.
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/* parameters are compile time directives
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this can be an any-width, any-depth reg_file: just override the params!
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*/
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module RegFile #(parameter W=8, D=4)( // W = data path width (leave at 8); D = address pointer width
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input Clk,
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Reset, // note use of Reset port
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WriteEn,
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input [D-1:0] RaddrA, // address pointers
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RaddrB,
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Waddr,
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input [W-1:0] DataIn,
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output [W-1:0] DataOutA, // showing two different ways to handle DataOutX, for
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output logic [W-1:0] DataOutB // pedagogic reasons only
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);
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// W bits wide [W-1:0] and 2**4 registers deep
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logic [W-1:0] Registers[2**D]; // or just registers[16] if we know D=4 always
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// combinational reads
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/* can use always_comb in place of assign
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difference: assign is limited to one line of code, so
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always_comb is much more versatile
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*/
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assign DataOutA = Registers[RaddrA]; // assign & always_comb do the same thing here
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always_comb DataOutB = Registers[RaddrB]; // can read from addr 0, just like ARM
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// sequential (clocked) writes
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always_ff @ (posedge Clk)
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if (Reset) begin
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for(int i=0; i<2**D; i++)
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Registers[i] <= 'h0;
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// we can override this universal clear command with desired initialization values
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Registers[0] <= 'd30; // loads 30 (=0x1E) into RegFile address 0
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Registers[2] <= 'b101; // loads 00000101 into RegFile address 2
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end
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else if (WriteEn) // works just like data_memory writes
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Registers[Waddr] <= DataIn;
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endmodule
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151
RTL/TopLevel.sv
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151
RTL/TopLevel.sv
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@ -0,0 +1,151 @@
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// Revision Date: 2022.05.05
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// Design Name: BasicProcessor
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// Module Name: TopLevel
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// CSE141L -- partial only
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module TopLevel( // you will have the same 3 ports
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input Reset, // init/reset, active high
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Start, // start next program
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Clk, // clock -- posedge used inside design
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output logic Ack // done flag from DUT
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);
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// program counter / instructon fetch connections
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wire [ 1:0] TargSel; // for branch LUT select
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wire [ 9:0] PgmCtr, // program counter (wider if you wish)
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PCTarg;
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wire [ 8:0] Instruction; // our 9-bit opcode
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// data path connections -- everything is 8 bits wide
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wire [ 7:0] ReadA, ReadB; // reg_file outputs
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wire [ 7:0] InA, InB, // ALU operand inputs
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ALU_out; // ALU result
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wire [ 7:0] RegWriteValue, // data in to reg file
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MemWriteValue, // data in to data_memory
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MemReadValue, // data out from data_memory
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DatMemAddr , //
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Immediate; //
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// control wires
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wire Imm, // inserts Immediate into ALU
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MemWrite, // data_memory write enable
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RegWrEn, // reg_file write enable
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Zero, // ALU output = 0 flag
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Jump, // to program counter: jump
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BranchEn; // to program counter: branch enable
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// ALU status register, analogous to ARM
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logic PFq, // delayed/stored parity bit from ALU
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SCq, // delayed/stored shift-carry out flag
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Zq; // delayed/stored null out flag from ALU
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logic[15:0] CycleCt; // standalone; NOT PC!
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// Fetch stage = Program Counter + Instruction ROM
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// "InstFetch" = PC register + branch/increment logic
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InstFetch IF1 ( // this is the program counter module
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.Reset (Reset ) , // reset to 0
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.Start (Start ) , // SystemVerilog shorthand for .grape(grape) is just .grape
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.Clk (Clk ) , // here, (Clk) is required in Verilog, optional in SystemVerilog
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.BranchAbs (Jump ) , // jump enable
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.BranchRelEn (BranchEn) , // branch enable
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.ALU_flag (Zero ) , //
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.Target (PCTarg ) , // "where to?" or "how far?" during a jump or branch
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.ProgCtr (PgmCtr ) // program count = index to instruction memory
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);
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LUT LUT1(.Addr (TargSel ) ,
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.Target (PCTarg )
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);
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// instruction ROM -- holds the machine code selected by program counter
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// don't change W(9); increase A(10) if your machine code exceeds 1K lines
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InstROM #(.W(9),.A(10)) IR1(
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.InstAddress (PgmCtr ) ,
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.InstOut (Instruction)
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);
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// Decode stage = Control Decoder + Reg_file
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// Control decoder
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Ctrl Ctrl1 (
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.Instruction (Instruction) , // from instr_ROM
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// outputs
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.Jump (Jump ) , // to PC to handle jump/branch instructions
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.BranchEn (BranchEn ) , // to PC
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.RegWrEn (RegWrEn ) , // register file write enable
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.MemWrEn (MemWrite ) , // data memory write enable
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.LoadInst (LoadInst ) , // selects memory vs ALU output as data input to reg_file
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.PCTarg (TargSel ) ,
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.tapSel (tapSel ) ,
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.DatMemAddr (DatMemAddr ) ,
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.Ack (Ack ) // "done" flag
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);
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// reg file -- don't change W(8); may increase to D(4)
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// I arbitrarily mapped to Instructon fields [5:3] and [2:0]
|
||||
// you do not have to do this!!!
|
||||
RegFile #(.W(8),.D(3)) RF1 ( // D(3) makes this 8 elements deep
|
||||
.Clk ,
|
||||
.WriteEn (RegWrEn) ,
|
||||
.RaddrA (Instruction[5:3]), // see hint below
|
||||
.RaddrB (Instruction[2:0]), // or perhaps (Instruction[2:0]+1);
|
||||
// by choosing Waddr = RaddrA, I am doing write-in-place operations
|
||||
// such as A = A+B, as opposed to C = A+B
|
||||
.Waddr (Instruction[5:3]), //3'b0 // mux above
|
||||
.DataIn (RegWriteValue) ,
|
||||
.DataOutA (ReadA ) ,
|
||||
.DataOutB (ReadB )
|
||||
);
|
||||
// a trick you MAY find useful:
|
||||
// use 2 instructon bits to select 2 adjacent addresses in RegFile
|
||||
// .RaddA ({Instruction[1:0],1'b0}),
|
||||
// .RaddB ({Instruction[1:0],1'b1}),
|
||||
|
||||
// logic[3:0] Tap_ptr; // tap pattern selector
|
||||
// sample LUT from a different program
|
||||
logic[7:0] Immediate; // tap pattern itself
|
||||
Immediate_LUT IL1(.addr(Instruction[5:3]), .datOut(Immediate));
|
||||
|
||||
assign InA = Imm? Immediate : ReadA; // connect RF out to ALU in
|
||||
assign InB = ReadB; // interject switch/mux if needed/desired
|
||||
assign MemWriteValue = ReadB;
|
||||
// controlled by Ctrl1 -- must be high for load from data_mem; otherwise usually low
|
||||
assign RegWriteValue = LoadInst? MemReadValue : ALU_out; // 2:1 switch into reg_file
|
||||
ALU ALU1 (
|
||||
.InputA (InA), //(ReadA),
|
||||
.InputB (InB),
|
||||
.SC_in (PFq), // registered version of output flag
|
||||
.OP (Instruction[8:6]),
|
||||
.Out (ALU_out),//regWriteValue),
|
||||
.PF (PF), // output parity status flag
|
||||
.Zero (Zero), // null output status flag
|
||||
.SC_out (SCout), // shift/carry output flag
|
||||
); // other flags as desired?
|
||||
|
||||
// equiv. to ARM ALU status register
|
||||
// store flags for next clock cycle
|
||||
always @(posedge Clk) begin
|
||||
SCq <= SCout;
|
||||
PFq <= PF;
|
||||
Zq <= Zero;
|
||||
end
|
||||
|
||||
DataMem DM1(
|
||||
.DataAddress (ReadA) ,
|
||||
.WriteEn (MemWrite),
|
||||
.DataIn (MemWriteValue),
|
||||
.DataOut (MemReadValue) ,
|
||||
.Clk (Clk) ,
|
||||
.Reset (Reset)
|
||||
);
|
||||
|
||||
//always_comb chosen_bit = MemReadValue[5:2];
|
||||
|
||||
/* count number of instructions executed
|
||||
not part of main design, potentially useful
|
||||
This one halts when Ack is high
|
||||
*/
|
||||
always_ff @(posedge Clk)
|
||||
if (Reset == 1) // if(start)
|
||||
CycleCt <= 0;
|
||||
else if(Ack == 0) // if(!halt)
|
||||
CycleCt <= CycleCt+16'b1;
|
||||
|
||||
endmodule
|
||||
78
RTL/TopLevelLab2.sv
Normal file
78
RTL/TopLevelLab2.sv
Normal file
@ -0,0 +1,78 @@
|
||||
// team name quarter
|
||||
module TopLevel( // you will have the same 3 ports
|
||||
input Reset, // init/reset, active high
|
||||
Start, // start next program
|
||||
Clk, // clock -- posedge used inside design
|
||||
output logic Ack // done flag from DUT
|
||||
);
|
||||
|
||||
|
||||
InstFetch IF1 ( // this is the program counter module
|
||||
.Reset (Reset ) , // reset to 0
|
||||
.Start (Start ) , // SystemVerilog shorthand for .grape(grape) is just .grape
|
||||
.Clk (Clk ) , // here, (Clk) is required in Verilog, optional in SystemVerilog
|
||||
.BranchAbs (Jump ) , // jump enable
|
||||
.BranchRelEn (BranchEn) , // branch enable
|
||||
.ALU_flag (Zero ) , //
|
||||
.Target (PCTarg ) , // "where to?" or "how far?" during a jump or branch
|
||||
.ProgCtr (PgmCtr ) // program count = index to instruction memory
|
||||
);
|
||||
|
||||
LUT LUT1(.Addr (TargSel ) ,
|
||||
.Target (PCTarg )
|
||||
);
|
||||
|
||||
|
||||
// instruction ROM -- holds the machine code pointed to by program counter
|
||||
InstROM #(.W(9),.A(10)) IR1(
|
||||
.InstAddress (PgmCtr ) ,
|
||||
.InstOut (Instruction)
|
||||
);
|
||||
|
||||
// in place c = a+c ADD R0 R1 R0
|
||||
// reg file
|
||||
RegFile #(.W(8),.D(3)) RF1 ( // D(3) makes this 8 elements deep
|
||||
.Clk ,
|
||||
.WriteEn (RegWrEn) ,
|
||||
.RaddrA (Instruction[5:3]), //3'b0 //concatenate with 0 to give us 4 bits
|
||||
.RaddrB (Instruction[2:0]), // (Instruction[2:0]+1);
|
||||
.Waddr (Instruction[5:3]), //3'b0 // mux above
|
||||
.DataIn (RegWriteValue) ,
|
||||
// outputs
|
||||
.DataOutA (ReadA ) ,
|
||||
.DataOutB (ReadB )
|
||||
);
|
||||
|
||||
ALU ALU1 (
|
||||
.InputA (InA),
|
||||
.InputB (InB),
|
||||
.SC_in (PFq),
|
||||
.OP (Instruction[8:6]),
|
||||
// outputs
|
||||
.Out (ALU_out),//regWriteValue),
|
||||
.PF (PF),
|
||||
.Zero // status flag; may have others, if desired
|
||||
);
|
||||
|
||||
always @(posedge Clk)
|
||||
PFq <= PF;
|
||||
|
||||
|
||||
DataMem DM1(
|
||||
// inputs
|
||||
.Clk (Clk) ,
|
||||
.Reset (Reset) ,
|
||||
.DataAddress (ReadA) ,
|
||||
.WriteEn (MemWrite),
|
||||
.DataIn (MemWriteValue),
|
||||
// outputs
|
||||
.DataOut (MemReadValue)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
71
RTL/TopLevel_tb.sv
Normal file
71
RTL/TopLevel_tb.sv
Normal file
@ -0,0 +1,71 @@
|
||||
// Create Date: 2017.01.25
|
||||
// Design Name: TopLevel Test Bench
|
||||
// Module Name: TopLevel_tb.v
|
||||
// CSE141L
|
||||
// This is NOT synthesizable; use for logic simulation only
|
||||
// Verilog Test Fixture created for module: TopLevel
|
||||
|
||||
module TopLevel_tb; // Lab 17
|
||||
|
||||
// To DUT Inputs
|
||||
bit Init = 'b1,
|
||||
Req, // start
|
||||
Clk; // logic Clk; // inits to 1'bx
|
||||
// logic Clk = 1'b0;
|
||||
|
||||
// From DUT Outputs
|
||||
wire Ack; // done flag
|
||||
|
||||
// Instantiate the Device Under Test (DUT)
|
||||
TopLevel DUT (
|
||||
.Reset (Init) ,
|
||||
.Start (Req ) ,
|
||||
.Clk (Clk ) ,
|
||||
.Ack (Ack )
|
||||
);
|
||||
|
||||
initial begin
|
||||
#10ns Init = 'b0;
|
||||
#10ns Req = 'b1;
|
||||
// Initialize DUT's data memory
|
||||
#10ns for(int i=0; i<256; i++) begin
|
||||
DUT.DM1.Core[i] = 8'h0; // clear data_mem
|
||||
end
|
||||
DUT.DM1.Core[1] = 8'h03; // MSW of operand A
|
||||
DUT.DM1.Core[2] = 8'hff;
|
||||
DUT.DM1.Core[3] = 8'hff; // MSW of operand B
|
||||
DUT.DM1.Core[4] = 8'hfb;
|
||||
DUT.DM1.Core[128] = 8'h00; // preload constants
|
||||
// ...
|
||||
DUT.DM1.Core[255] = 8'h00;
|
||||
// students may also pre_load desired constants into DM
|
||||
// Initialize DUT's register file
|
||||
for(int j=0; j<16; j++)
|
||||
DUT.RF1.Registers[j] = 8'b0; // default -- clear it
|
||||
// students may pre-load desired constants into the reg_file
|
||||
// $readmemb("machine_code.txt",inst);
|
||||
// for(int k=0; k<1024; k++)
|
||||
// DUT.IR1.inst_rom[k] = inst[k];
|
||||
|
||||
|
||||
// launch prodvgram in DUT
|
||||
#10ns Req = 0;
|
||||
// Wait for done flag, then display results
|
||||
wait (Ack);
|
||||
#10ns $displayh(DUT.DM1.Core[5],
|
||||
DUT.DM1.Core[6],"_",
|
||||
DUT.DM1.Core[7],
|
||||
DUT.DM1.Core[8]);
|
||||
// $display("instruction = %d %t",DUT.PC,$time);
|
||||
#10ns $stop; // $finish;
|
||||
end
|
||||
|
||||
always begin // clock period = 10 Verilog time units
|
||||
#5ns Clk = 'b1;
|
||||
#5ns Clk = 'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
// always #5ns Clk = ~Clk;
|
||||
34
RTL/prog_ctr2.sv
Normal file
34
RTL/prog_ctr2.sv
Normal file
@ -0,0 +1,34 @@
|
||||
// Design Name: basic_proc
|
||||
// Module Name: InstFetch
|
||||
// Project Name: CSE141L
|
||||
// Description: instruction fetch (pgm ctr) for processor
|
||||
//
|
||||
// Revision: 2019.01.27
|
||||
//
|
||||
module InstFetch(
|
||||
input Reset, // reset, init, etc. -- force PC to 0
|
||||
Start, // begin next program in series (request issued by test bench)
|
||||
Clk, // PC can change on pos. edges only
|
||||
BranchAbs, // jump unconditionally to Target value
|
||||
ALU_flag, // flag from ALU, e.g. Zero, Carry, Overflow, Negative (from ARM)
|
||||
input [9:0] Target, // jump ... "how high?"
|
||||
output logic [9:0] ProgCtr // the program counter register itself
|
||||
);
|
||||
|
||||
// program counter can clear to 0, increment, or jump
|
||||
always_ff @(posedge Clk) // or just always; always_ff is a linting construct
|
||||
if(Reset)
|
||||
ProgCtr <= 0; // for first program; want different value for 2nd or 3rd
|
||||
else if(Start) // hold while start asserted; commence when released
|
||||
ProgCtr <= 0;//ProgCtr;
|
||||
else if(BranchAbs) // unconditional absolute jump
|
||||
ProgCtr <= Target; // how would you make it conditional and/or relative?
|
||||
else
|
||||
ProgCtr <= ProgCtr+'b1; // default increment (no need for ARM/MIPS +4 -- why?)
|
||||
|
||||
endmodule
|
||||
|
||||
/* Note about Start: if your programs are spread out, with a gap in your machine code listing, you will want
|
||||
to make Start cause an appropriate jump. If your programs are packed sequentially, such that program 2 begins
|
||||
right after Program 1 ends, then you won't need to do anything special here.
|
||||
*/
|
||||
Reference in New Issue
Block a user