34 lines
1.6 KiB
Systemverilog
34 lines
1.6 KiB
Systemverilog
// Design Name: basic_proc
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// Module Name: InstFetch
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// Project Name: CSE141L
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// Description: instruction fetch (pgm ctr) for processor
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//
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// Revision: 2019.01.27
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//
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module InstFetch(
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input Reset, // reset, init, etc. -- force PC to 0
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Start, // begin next program in series (request issued by test bench)
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Clk, // PC can change on pos. edges only
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BranchAbs, // jump unconditionally to Target value
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ALU_flag, // flag from ALU, e.g. Zero, Carry, Overflow, Negative (from ARM)
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input [9:0] Target, // jump ... "how high?"
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output logic [9:0] ProgCtr // the program counter register itself
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);
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// program counter can clear to 0, increment, or jump
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always_ff @(posedge Clk) // or just always; always_ff is a linting construct
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if(Reset)
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ProgCtr <= 0; // for first program; want different value for 2nd or 3rd
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else if(Start) // hold while start asserted; commence when released
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ProgCtr <= 0;//ProgCtr;
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else if(BranchAbs) // unconditional absolute jump
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ProgCtr <= Target; // how would you make it conditional and/or relative?
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else
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ProgCtr <= ProgCtr+'b1; // default increment (no need for ARM/MIPS +4 -- why?)
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endmodule
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/* Note about Start: if your programs are spread out, with a gap in your machine code listing, you will want
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to make Start cause an appropriate jump. If your programs are packed sequentially, such that program 2 begins
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right after Program 1 ends, then you won't need to do anything special here.
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*/ |