25 lines
805 B
Systemverilog
25 lines
805 B
Systemverilog
//This file defines the parameters used in the alu
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// CSE141L
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// Rev. 2020.5.27
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// import package into each module that needs it
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// packages very useful for declaring global variables
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package definitions;
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/* Instruction map
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const logic [2:0]kADD = 3'b000;
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const logic [2:0]kLSH = 3'b001;
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const logic [2:0]kRSH = 3'b010;
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const logic [2:0]kXOR = 3'b011;
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const logic [2:0]kAND = 3'b100;
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const logic [2:0]kSUB = 3'b101;
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const logic [2:0]kCLR = 3'b110;
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*/
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// enum names will appear in timing diagram
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typedef enum logic[2:0] {
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ADD, LSH, BSH, XOR,
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AND, SUB, CLR } op_mne;
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// note: kADD is of type logic[2:0] (3-bit binary)
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// ADD is of type enum -- equiv., but watch casting
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// see ALU.sv for how to handle this
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endpackage // definitions
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