55 lines
1.8 KiB
Systemverilog
55 lines
1.8 KiB
Systemverilog
// Create Date: 2018.10.15
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// Module Name: ALU
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// Project Name: CSE141L
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//
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// Revision 2022.04.30
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// Additional Comments:
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// combinational (unclocked) ALU
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import definitions::*; // includes package "definitions"
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module ALU #(parameter W=8)(
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input [W-1:0] InputA, // data inputs
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InputB,
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input SC_in, // shift or carry in
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input [ 2:0] OP, // ALU opcode, part of microcode
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output logic [W-1:0] Out, // or: output reg [7:0] OUT,
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output logic PF, // reduction parity
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output logic Zero, // output = zero flag
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output logic SC_out // shift or carry out
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// you may provide additional status flags as inputs, if desired
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);
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op_mne op_mnemonic; // type enum: used for convenient waveform viewing
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// InputA = current LFSR state
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// InputB = tap_pattern
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always_comb begin
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Out = 0;
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SC_out = 0; // No Op = default
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case(OP)
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kADD : {SC_out,Out} = {1'b0,InputA} + InputB; // add
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kLSH : {SC_out,Out} = {InputA[7:0],SC_in}; // shift left, fill in with SC_in
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// for logical left shift, tie SC_in = 0
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kRSH : {Out,SC_out} = {SC_in, InputA[7:0]}; // shift right
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kXOR : Out = InputA ^ InputB; // exclusive OR
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kAND : Out = InputA & InputB; // bitwise AND
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endcase
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end
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always_comb // assign Zero = !Out;
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case(Out)
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'b0 : Zero = 1'b1;
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default : Zero = 1'b0;
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endcase
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always_comb
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PF = ^Out; // Out[7]^Out[6]^...^Out[0] // reduction XOR
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always_comb
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op_mnemonic = op_mne'(OP); // displays operation name in waveform viewer
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endmodule
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/* InputA=10101010 SC_in = 1
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kLSH Out = 01010101
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*/ |