78 lines
2.1 KiB
Systemverilog
78 lines
2.1 KiB
Systemverilog
// team name quarter
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module TopLevel( // you will have the same 3 ports
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input Reset, // init/reset, active high
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Start, // start next program
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Clk, // clock -- posedge used inside design
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output logic Ack // done flag from DUT
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);
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InstFetch IF1 ( // this is the program counter module
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.Reset (Reset ) , // reset to 0
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.Start (Start ) , // SystemVerilog shorthand for .grape(grape) is just .grape
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.Clk (Clk ) , // here, (Clk) is required in Verilog, optional in SystemVerilog
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.BranchAbs (Jump ) , // jump enable
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.BranchRelEn (BranchEn) , // branch enable
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.ALU_flag (Zero ) , //
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.Target (PCTarg ) , // "where to?" or "how far?" during a jump or branch
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.ProgCtr (PgmCtr ) // program count = index to instruction memory
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);
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LUT LUT1(.Addr (TargSel ) ,
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.Target (PCTarg )
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);
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// instruction ROM -- holds the machine code pointed to by program counter
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InstROM #(.W(9),.A(10)) IR1(
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.InstAddress (PgmCtr ) ,
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.InstOut (Instruction)
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);
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// in place c = a+c ADD R0 R1 R0
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// reg file
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RegFile #(.W(8),.D(3)) RF1 ( // D(3) makes this 8 elements deep
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.Clk ,
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.WriteEn (RegWrEn) ,
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.RaddrA (Instruction[5:3]), //3'b0 //concatenate with 0 to give us 4 bits
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.RaddrB (Instruction[2:0]), // (Instruction[2:0]+1);
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.Waddr (Instruction[5:3]), //3'b0 // mux above
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.DataIn (RegWriteValue) ,
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// outputs
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.DataOutA (ReadA ) ,
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.DataOutB (ReadB )
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);
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ALU ALU1 (
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.InputA (InA),
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.InputB (InB),
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.SC_in (PFq),
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.OP (Instruction[8:6]),
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// outputs
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.Out (ALU_out),//regWriteValue),
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.PF (PF),
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.Zero // status flag; may have others, if desired
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);
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always @(posedge Clk)
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PFq <= PF;
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DataMem DM1(
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// inputs
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.Clk (Clk) ,
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.Reset (Reset) ,
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.DataAddress (ReadA) ,
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.WriteEn (MemWrite),
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.DataIn (MemWriteValue),
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// outputs
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.DataOut (MemReadValue)
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);
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endmodule |