71 lines
1.9 KiB
Systemverilog
71 lines
1.9 KiB
Systemverilog
// Create Date: 2017.01.25
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// Design Name: TopLevel Test Bench
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// Module Name: TopLevel_tb.v
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// CSE141L
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// This is NOT synthesizable; use for logic simulation only
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// Verilog Test Fixture created for module: TopLevel
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module TopLevel_tb; // Lab 17
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// To DUT Inputs
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bit Init = 'b1,
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Req, // start
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Clk; // logic Clk; // inits to 1'bx
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// logic Clk = 1'b0;
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// From DUT Outputs
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wire Ack; // done flag
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// Instantiate the Device Under Test (DUT)
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TopLevel DUT (
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.Reset (Init) ,
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.Start (Req ) ,
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.Clk (Clk ) ,
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.Ack (Ack )
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);
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initial begin
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#10ns Init = 'b0;
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#10ns Req = 'b1;
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// Initialize DUT's data memory
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#10ns for(int i=0; i<256; i++) begin
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DUT.DM1.Core[i] = 8'h0; // clear data_mem
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end
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DUT.DM1.Core[1] = 8'h03; // MSW of operand A
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DUT.DM1.Core[2] = 8'hff;
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DUT.DM1.Core[3] = 8'hff; // MSW of operand B
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DUT.DM1.Core[4] = 8'hfb;
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DUT.DM1.Core[128] = 8'h00; // preload constants
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// ...
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DUT.DM1.Core[255] = 8'h00;
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// students may also pre_load desired constants into DM
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// Initialize DUT's register file
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for(int j=0; j<16; j++)
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DUT.RF1.Registers[j] = 8'b0; // default -- clear it
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// students may pre-load desired constants into the reg_file
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// $readmemb("machine_code.txt",inst);
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// for(int k=0; k<1024; k++)
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// DUT.IR1.inst_rom[k] = inst[k];
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// launch prodvgram in DUT
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#10ns Req = 0;
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// Wait for done flag, then display results
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wait (Ack);
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#10ns $displayh(DUT.DM1.Core[5],
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DUT.DM1.Core[6],"_",
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DUT.DM1.Core[7],
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DUT.DM1.Core[8]);
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// $display("instruction = %d %t",DUT.PC,$time);
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#10ns $stop; // $finish;
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end
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always begin // clock period = 10 Verilog time units
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#5ns Clk = 'b1;
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#5ns Clk = 'b0;
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end
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endmodule
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// always #5ns Clk = ~Clk;
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