40 lines
1.5 KiB
Systemverilog
40 lines
1.5 KiB
Systemverilog
// Create Date: 2017.01.25
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// Revision: 2022.05.04 made data width parametric
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// Design Name:
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// Module Name: DataMem
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// single address pointer for both read and write
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// CSE141L
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module DataMem #(parameter W=8, D=8)(
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input Clk,
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Reset, // again, note use of Reset for preloads
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WriteEn,
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input [D-1:0] DataAddress, // 8-bit-wide pointer to 256-deep memory
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input [W-1:0] DataIn, // 8-bit-wide data path, also
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output logic[W-1:0] DataOut);
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logic [W-1:0] Core[2**D]; // 8x256 two-dimensional array -- the memory itself
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always_comb // reads are combinational
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DataOut = Core[DataAddress];
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/* optional way to plant constants into DataMem at startup
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initial
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$readmemh("dataram_init.list", Core);
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*/
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always_ff @ (posedge Clk) // writes are sequential
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/*( Reset response is needed only for initialization (see inital $readmemh above for another choice)
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if you do not need to preload your data memory with any constants, you may omit the if(Reset) and the else,
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and go straight to if(WriteEn) ...
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*/
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if(Reset) begin
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// you may initialize your memory w/ constants, if you wish
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for(int i=128;i<256;i++)
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Core[ i] <= 0;
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Core[ 16] <= 254; // overrides the 0 ***sample only***
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Core[244] <= 5; // likewise
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end
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else if(WriteEn)
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Core[DataAddress] <= DataIn;
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endmodule
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