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cse141L-project/RTL/Ctrl.sv

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// Module Name: Ctrl
// Project Name: CSE141L
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// control decoder (combinational, not clocked)
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import Definitions::*;
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module Ctrl #(
parameter W = 8,
parameter T = 10
) (
input logic [8:0] Instruction,
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input logic [W-1:0] ALU_Out,
input logic [W-1:0] RegOutA, RegOutB, // select from register inputs or immediate inputs
input logic [T-1:0] ProgCtr_p1,
input logic [W-1:0] mem_out,
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output op_mne ALU_OP, // control ALU operation
output logic [W-1:0] ALU_A, ALU_B,
output logic RegWrite, Done_in,
output logic [3:0] RaddrA, RaddrB, Waddr,
output logic [W-1:0] RegInput,
output logic BranchEZ, BranchNZ, BranchAlways,
output logic write_mem
);
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logic [7:0] I_Immediate;
logic [7:0] T_Immediate;
logic [3:0] A_operand;
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assign I_Immediate = Instruction[7:0];
assign T_Immediate = Instruction[2:0];
assign A_operand = Instruction[3:0];
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always_comb begin
// default values for an invalid NOP instruction, proper NOP instruction encoded as a LSH by 0
ALU_OP = NOP;
ALU_A = RegOutA;
ALU_B = RegOutB;
RegWrite = 'b1;
Done_in = 'b0;
RaddrA = 'b0;
RaddrB = 'b0;
Waddr = 'b0;
RegInput = ALU_Out;
BranchEZ = 'b0;
BranchNZ = 'b0;
BranchAlways = 'b0;
write_mem = 'b0;
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if(Instruction[8]) begin
ALU_A = I_Immediate;
end
else case(Instruction[7:4])
'b0000: begin // PUT
Waddr = A_operand;
end
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'b0001: begin // GET
RaddrA = A_operand;
end
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'b0010: begin // LDW
RaddrA = A_operand;
RegInput = mem_out;
end
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'b0011: begin // STW
RaddrA = A_operand;
RegWrite = 'b0;
write_mem = 'b1;
end
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'b0100: begin // NXT
if(A_operand == 'd8 || A_operand == 'd9 || A_operand == 'd10) begin
ALU_OP = SUB;
ALU_B = 'b1;
end
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else if (A_operand == 'd11 || A_operand == 'd12 || A_operand == 'd13) begin
ALU_OP = ADD;
ALU_B = 'b1;
end
else ALU_OP = NOP;
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RaddrA = A_operand;
Waddr = A_operand;
end
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'b0101: begin //CLB
ALU_OP = CLB;
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RaddrA = A_operand;
Waddr = A_operand;
end
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'b0110: begin // ADD
ALU_OP = ADD;
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RaddrA = A_operand;
end
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'b0111: begin // AND
ALU_OP = AND;
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RaddrA = A_operand;
end
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'b1000: begin // LSH
ALU_OP = LSH;
ALU_A = T_Immediate;
end
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'b1001: begin // RXR
ALU_OP = RXOR;
RaddrA = A_operand;
end
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'b1010: begin // XOR
ALU_OP = XOR;
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RaddrA = A_operand;
end
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'b1011: begin // DNE
Done_in = 'b1;
end
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'b1100: begin // JNZ
RegWrite = 'b0;
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RaddrA = A_operand;
BranchNZ = 'b1;
end
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'b1101: begin // JEZ
RegWrite = 'b0;
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RaddrA = A_operand;
BranchEZ = 'b1;
end
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'b1110: begin // JMP
RegWrite = 'b0;
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RaddrA = A_operand;
BranchAlways = 'b1;
end
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'b1111: begin // JAL
RaddrA = A_operand;
Waddr = 'd14; // write to link register specifically
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RegInput = ProgCtr_p1[7:0]; // write the value pc+4
BranchAlways = 'b1;
end
endcase
end
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endmodule