57 lines
1.7 KiB
Systemverilog
57 lines
1.7 KiB
Systemverilog
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// CSE141L
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import definitions::*;
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// control decoder (combinational, not clocked)
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// inputs from instrROM, ALU flags
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// outputs to program_counter (fetch unit)
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module Ctrl (
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input[ 8:0] Instruction, // machine code
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input[ 7:0] DatMemAddr,
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output logic Jump ,
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BranchEn ,
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RegWrEn , // write to reg_file (common)
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MemWrEn , // write to mem (store only)
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LoadInst , // mem or ALU to reg_file ?
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PCTarg ,
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tapSel ,
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Ack // "done w/ program"
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// output logic[2:0] ALU_inst
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);
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/* ***** All numerical values are completely arbitrary and for illustration only *****
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*/
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// ALU commands
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//assign ALU_inst = Instruction[2:0];
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// STR commands only -- write to data_memory
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assign MemWrEn = Instruction[8:6]==3'b110;
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// all but STR and NOOP (or maybe CMP or TST) -- write to reg_file
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assign RegWrEn = Instruction[8:7]!=2'b11;
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// route data memory --> reg_file for loads
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// whenever instruction = 9'b110??????;
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assign LoadInst = Instruction[8:6]==3'b110; // calls out load specially
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assign tapSel = LoadInst && DatMemAddr=='d62;
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// jump enable command to program counter / instruction fetch module on right shift command
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// equiv to simply: assign Jump = Instruction[2:0] == kRSH;
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always_comb
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if(Instruction[2:0] == kRSH)
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Jump = 1;
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else
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Jump = 0;
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// branch every time instruction = 9'b?????1111;
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assign BranchEn = &Instruction[3:0];
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// whenever branch or jump is taken, PC gets updated or incremented from "Target"
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// PCTarg = 2-bit address pointer into Target LUT (PCTarg in --> Target out
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assign PCTarg = Instruction[3:2];
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// reserve instruction = 9'b111111111; for Ack
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assign Ack = &Instruction;
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endmodule
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