implement control comb logic (untested)
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Arthur Lu
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2f967bef04
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@ -21,7 +21,7 @@ module ALU #(parameter W=8)(
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SUB: Out = A - B; // subtract B from A
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ORR: Out = A | B; // bitwise OR between A and B
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AND: Out = A & B; // bitwise AND between A and B
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LSH: Out = A << B; // shift A by B bits
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LSH: Out = B << A; // shift B by A bits (limitation of control)
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RXOR_7: Out = ^(A[6:0]); // perform reduction XOR of lower 7 bits of A
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RXOR_8: Out = ^(A[7:0]); // perform reduction XOR of lower 8 bits of A
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XOR: Out = A ^ B; // bitwise XOR between A and B
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207
RTL/Ctrl.sv
207
RTL/Ctrl.sv
@ -1,84 +1,143 @@
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// CSE141L
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import Definitions::*;
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// Module Name: ALU
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// Project Name: CSE141L
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// control decoder (combinational, not clocked)
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// inputs from instrROM, ALU flags
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// outputs to program_counter (fetch unit)
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module Ctrl (
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input[ 8:0] Instruction, // machine code
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input[ 7:0] DatMemAddr,
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output logic Branch ,
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BranchEn ,
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RegWrEn , // write to reg_file (common)
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MemWrEn , // write to mem (store only)
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LoadInst , // mem or ALU to reg_file ?
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TapSel ,
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Ack , // "done w/ program"
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output logic[1:0] PCTarg,
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// output logic[2:0] ALU_inst
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);
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/* ***** All numerical values are completely arbitrary and for illustration only *****
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*/
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import Definitions::*;
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// alternative -- case format
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always_comb begin
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// list the defaults here
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Branch = 'b0;
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BranchEn = 'b0;
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RegWrEn = 'b1;
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MemWrEn = 'b0;
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LoadInst = 'b0;
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TapSel ' 'b0; //
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PCTarg = 'b0; // branch "where to?"
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case(Instruction[8:6]) // list just the exceptions
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3'b000: begin
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MemWrEn = 'b1; // store, maybe
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RegWrEn = 'b0;
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end
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3'b001: LoadInst = 'b1; // load
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3'b010: begin end
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3'b011: begin end
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3'b100: begin end
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3'b101: begin end
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3'b110: begin end
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// no default case needed -- covered before "case"
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endcase
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end
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module Ctrl #(
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parameter W = 8,
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parameter T = 10
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) (
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input logic [8:0] Instruction,
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input logic [W-1:0] ALU_Out, // control ALU operation
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input logic [W-1:0] RegOutA, RegOutB, // select from register inputs or immediate inputs
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input logic [T-1:0] ProgCtr_p4,
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input logic [W-1:0] mem_out,
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output op_mne ALU_OP,
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output logic [W-1:0] ALU_A, ALU_B,
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output logic RegWrite, Done_in,
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output logic [3:0] RaddrA, RaddrB, Waddr, RegInput,
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output logic BranchEZ, BranchNZ, BranchAlways,
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output logic write_mem
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);
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assign Ack = ProgCtr == 971;
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// alternative Ack = Instruction == 'b111_000_111
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logic [7:0] I_Immediate;
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logic [7:0] T_Immediate;
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logic [3:0] A_operand;
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logic [3:0] S_operand;
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logic [3:0] G_operand;
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// ALU commands
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//assign ALU_inst = Instruction[2:0];
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assign I_Immediate = Instruction[7:0];
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assign T_Immediate = Instruction[2:0];
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assign A_operand = Instruction[3:0];
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assign S_operand = {'b1, Instruction[2:0]};
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assign G_operand = {'b0, Instruction[2:0]};
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// STR commands only -- write to data_memory
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assign MemWrEn = Instruction[8:6]==3'b110;
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assign ALU_B = RegOutB;
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// all but STR and NOOP (or maybe CMP or TST) -- write to reg_file
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assign RegWrEn = Instruction[8:7]!=2'b11;
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// route data memory --> reg_file for loads
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// whenever instruction = 9'b110??????;
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assign LoadInst = Instruction[8:6]==3'b110; // calls out load specially
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assign tapSel = LoadInst && DatMemAddr=='d62;
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// jump enable command to program counter / instruction fetch module on right shift command
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// equiv to simply: assign Jump = Instruction[2:0] == RSH;
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always_comb
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if(Instruction[2:0] == RSH)
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Branch = 1;
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else
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Branch = 0;
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// branch every time instruction = 9'b?????1111;
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assign BranchEn = &Instruction[3:0];
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// whenever branch or jump is taken, PC gets updated or incremented from "Target"
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// PCTarg = 2-bit address pointer into Target LUT (PCTarg in --> Target out
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assign PCTarg = Instruction[3:2];
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// reserve instruction = 9'b111111111; for Ack
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assign Ack = &Instruction; // = ProgCtr == 385;
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always_comb begin
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// default values for an invalid NOP instruction, proper NOP instruction encoded as a LSH by 0
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ALU_OP = NOP;
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ALU_A = RegOutA;
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RegWrite = 'b1;
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Done_in = 'b0;
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RaddrA = 'b0;
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RaddrB = 'b0;
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Waddr = 'b0;
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RegInput = ALU_Out;
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BranchEZ = 'b0;
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BranchNZ = 'b0;
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BranchAlways = 'b0;
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write_mem = 'b0;
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casez(Instruction)
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'b1_xxxx_xxxx: begin // LDI
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ALU_A = I_Immediate;
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end
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'b0_0000_xxxx: begin // PUT
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Waddr = A_operand;
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end
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'b0_0001_xxxx: begin // GET
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RaddrA = A_operand;
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end
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'b0_0010_0xxx: begin // LDW
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RaddrA = S_operand;
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RegInput = mem_out;
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end
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'b0_0010_1xxx: begin // STW
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RaddrA = S_operand;
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RegWrite = 'b0;
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write_mem = 'b1;
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end
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'b0_0011_0xxx: begin // NXT
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if(S_operand == 'd8 || S_operand == 'd9 || S_operand == d'10) ALU_OP = INC;
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else if (S_operand == 'd11 || S_operand == 'd12 || S_operand == d'13) ALU_OP = DEC;
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else ALU_OP = NOP;
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RaddrA = S_operand;
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Waddr = S_operand;
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end
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'b0_0011_1xxx: begin //CLB
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ALU_OP = CLB;
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RaddrA = G_operand;
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Waddr = G_operand;
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end
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'b0_0100_xxxx: begin // ADD
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ALU_OP = ADD;
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RaddrB = A_operand;
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end
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'b0_0101_xxxx: begin // SUB
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ALU_OP = SUB;
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RaddrB = A_operand;
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end
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'b0_0110_xxxx: begin // ORR
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ALU_OP = ORR;
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RaddrB = A_operand;
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end
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'b0_0111_xxxx: begin // AND
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ALU_OP = AND;
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RaddrB = A_operand;
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end
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'b0_1000_0xxx: begin // LSH
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ALU_OP = LSH;
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ALU_A = T_Immediate;
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end
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'b0_1000_1xxx: begin // PTY
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ALU_OP = RXOR_7;
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RaddrA = G_operand;
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end
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'b0_1001_xxxx: begin // CHK
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ALU_OP = RXOR_8;
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RaddrA = A_operand;
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end
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'b0_1010_xxxx: begin // XOR
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ALU_OP = XOR;
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RaddrB = A_operand;
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end
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'b0_1011_xxxx: begin // DNE
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Done_in = 'b1;
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end
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'b0_1110_0xxx: begin // JNZ
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RegWrite = 'b0;
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RaddrA = G_operand;
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BranchNZ = 'b1;
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end
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'b0_1110_1xxx: begin // JEZ
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RegWrite = 'b0;
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RaddrA = G_operand;
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BranchEZ = 'b1;
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end
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'b0_1111_0xxx: begin // JMP
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RegWrite = 'b0;
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RaddrA = G_operand;
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BranchAlways = 'b1;
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end
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'b0_1111_1xxx: begin // JAL
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RaddrA = G_operand;
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Waddr = 'd14; // write to link register specifically
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RegInput = ProgCtr_p4; // write the value pc+4
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BranchAlways = 'b1;
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end
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endcase
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end
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endmodule
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@ -1,17 +1,7 @@
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// Create Date: 2017.01.25
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// Design Name: CSE141L
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// Module Name: DataMem
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// Last Update: 2022.01.13
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// Module Name: ALU
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// Project Name: CSE141L
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// control decoder (combinational, not clocked)
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// Memory can only read (LDR) or write (STR) on each Clk cycle, so there is a single
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// address pointer for both read and write operations.
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//
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// Parameters:
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// - A: Address Width. This controls the number of entries in memory
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// - W: Data Width. This controls the size of each entry in memory
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// This memory can hold `(2**A) * W` bits of data.
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//
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// WI22 is a 256-entry single-byte (8 bit) data memory.
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module DataMem #(parameter W=8, A=8) ( // do not change W=8
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input Clk,
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Reset, // initialization
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@ -40,10 +30,10 @@ always_ff @ (posedge Clk)
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if(Reset) begin
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// Preload desired constants into data_mem[128:255]
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core[128] <= 'b1;
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core[129] <= 'hff;
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core[130] <= 'd64;
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end
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//core[128] <= 'b1;
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//core[129] <= 'hff;
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//core[130] <= 'd64;
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end
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else if(WriteEn) // store
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// Do the actual writes
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core[DataAddress] <= DataIn;
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@ -26,6 +26,8 @@ module RegFile #(parameter W=8, D=4)( // W = data path width (leave at 8); D =
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for(int i=0; i<2**D; i++) begin
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Registers[i] <= 'h0;
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end
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Zero <= 0;
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Done <= 1; // default Done to halt machine
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end
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else if (WriteEn) begin
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Registers[Waddr] <= DataIn;
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