combine PTY and CHK instruction,
recode remaining operands
This commit is contained in:
Arthur Lu
parent
218445e20c
commit
8e6962ad4d
@ -37,8 +37,7 @@ module ALU #(parameter W=8)(
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end
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AND: Out = A & B; // bitwise AND between A and B
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LSH: Out = B << A; // shift B by A bits (limitation of control)
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RXOR_7: Out = ^(A[6:0]); // perform reduction XOR of lower 7 bits of A
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RXOR_8: Out = ^(A[7:0]); // perform reduction XOR of lower 8 bits of A
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RXOR: Out = ^(A[7:0]); // perform reduction XOR of 8 bits of A
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XOR: Out = A ^ B; // bitwise XOR between A and B
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default: Out = 'bx; // flag illegal ALU_OP values
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endcase
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42
RTL/Ctrl.sv
42
RTL/Ctrl.sv
@ -49,26 +49,26 @@ module Ctrl #(
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BranchNZ = 'b0;
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BranchAlways = 'b0;
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write_mem = 'b0;
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casez(Instruction[8:3])
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'b1_????_?: begin // LDI
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casez(Instruction[8:4])
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'b1_????: begin // LDI
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ALU_A = I_Immediate;
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end
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'b0_0000_?: begin // PUT
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'b0_0000: begin // PUT
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Waddr = A_operand;
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end
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'b0_0001_?: begin // GET
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'b0_0001: begin // GET
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RaddrA = A_operand;
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end
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'b0_0010_0: begin // LDW
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'b0_0010: begin // LDW
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RaddrA = S_operand;
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RegInput = mem_out;
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end
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'b0_0010_1: begin // STW
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'b0_0011: begin // STW
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RaddrA = S_operand;
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RegWrite = 'b0;
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write_mem = 'b1;
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end
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'b0_0011_0: begin // NXT
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'b0_0100: begin // NXT
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if(S_operand == 'd8 || S_operand == 'd9 || S_operand == 'd10) begin
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ALU_OP = SUB;
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ALU_B = 'b1;
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@ -81,54 +81,50 @@ module Ctrl #(
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RaddrA = S_operand;
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Waddr = S_operand;
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end
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'b0_0011_1: begin //CLB
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'b0_0101: begin //CLB
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ALU_OP = CLB;
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RaddrA = G_operand;
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Waddr = G_operand;
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end
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'b0_0100_?: begin // ADD
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'b0_0110: begin // ADD
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ALU_OP = ADD;
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RaddrA = A_operand;
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end
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'b0_0111_?: begin // AND
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'b0_0111: begin // AND
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ALU_OP = AND;
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RaddrA = A_operand;
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end
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'b0_1000_0: begin // LSH
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'b0_1000: begin // LSH
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ALU_OP = LSH;
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ALU_A = T_Immediate;
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end
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'b0_1000_1: begin // PTY
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ALU_OP = RXOR_7;
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RaddrA = G_operand;
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end
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'b0_1001_?: begin // CHK
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ALU_OP = RXOR_8;
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'b0_1001: begin // RXR
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ALU_OP = RXOR;
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RaddrA = A_operand;
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end
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'b0_1010_?: begin // XOR
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'b0_1010: begin // XOR
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ALU_OP = XOR;
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RaddrA = A_operand;
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end
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'b0_1011_?: begin // DNE
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'b0_1011: begin // DNE
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Done_in = 'b1;
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end
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'b0_1110_0: begin // JNZ
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'b0_1100: begin // JNZ
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RegWrite = 'b0;
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RaddrA = G_operand;
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BranchNZ = 'b1;
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end
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'b0_1110_1: begin // JEZ
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'b0_1101: begin // JEZ
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RegWrite = 'b0;
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RaddrA = G_operand;
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BranchEZ = 'b1;
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end
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'b0_1111_0: begin // JMP
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'b0_1110: begin // JMP
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RegWrite = 'b0;
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RaddrA = G_operand;
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BranchAlways = 'b1;
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end
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'b0_1111_1: begin // JAL
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'b0_1111: begin // JAL
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RaddrA = G_operand;
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Waddr = 'd14; // write to link register specifically
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RegInput = ProgCtr_p1[7:0]; // write the value pc+4
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@ -14,8 +14,7 @@ package Definitions;
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ORR, // bitwise OR
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AND, // bitwise AND
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LSH, // left shift
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RXOR_7, // reduction XOR with lower 7 bits
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RXOR_8, // reduction XOR with lower 8 bits
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RXOR, // reduction xor
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XOR // bitwise XOR
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} op_mne;
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@ -34,12 +34,9 @@ op_type = {
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'NXT': 'S',
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'CLB': 'G',
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'ADD': 'A',
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#'SUB': 'A',
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#'ORR': 'A',
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'AND': 'A',
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'LSH': 'T',
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'PTY': 'G',
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'CHK': 'A',
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'RXR': 'G',
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'XOR': 'A',
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'DNE': 'N',
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'JNZ': 'G',
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@ -53,22 +50,19 @@ op_codes = {
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'PUT': 0b0_0000_0000,
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'GET': 0b0_0001_0000,
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'LDW': 0b0_0010_0000,
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'STW': 0b0_0010_1000,
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'NXT': 0b0_0011_0000,
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'CLB': 0b0_0011_1000,
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'ADD': 0b0_0100_0000,
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#'SUB': 0b0_0101_0000,
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#'ORR': 0b0_0110_0000,
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'STW': 0b0_0011_0000,
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'NXT': 0b0_0100_0000,
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'CLB': 0b0_0101_0000,
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'ADD': 0b0_0110_0000,
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'AND': 0b0_0111_0000,
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'LSH': 0b0_1000_0000,
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'PTY': 0b0_1000_1000,
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'CHK': 0b0_1001_0000,
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'RXR': 0b0_1001_0000,
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'XOR': 0b0_1010_0000,
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'DNE': 0b0_1011_1111,
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'JNZ': 0b0_1110_0000,
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'JEZ': 0b0_1110_1000,
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'JMP': 0b0_1111_0000,
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'JAL': 0b0_1111_1000,
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'DNE': 0b0_1011_1111,
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'JNZ': 0b0_1100_0000,
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'JEZ': 0b0_1101_0000,
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'JMP': 0b0_1110_0000,
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'JAL': 0b0_1111_0000,
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'NOP': 0b0_1000_0000
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}
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@ -52,7 +52,8 @@ main_loop: LDW r11 // load the next plaintext byte
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JMP r0 // jump to main_loop if there is still space for message characters
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lfsr_routine: GET r7 // get previous state
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AND r6 // and state with taps to get feedback pattern
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PTY r0 // get feedback parity bit
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CLB r0
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RXR r0 // get feedback parity bit
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PUT r1 // store feedback bit to r1 temporarily
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GET r7 // get previous state again
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LSH #d1 // left shift previous state by 1
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@ -94,7 +94,8 @@ main_loop: LDI lfsr_routine // load address for the lfsr_routine label
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JMP r0 // jump to main_loop if there is still space for message characters
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lfsr_routine: GET r7 // get previous state
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AND r6 // and state with taps to get feedback pattern
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PTY r0 // get feedback parity bit
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CLB r0
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RXR r0 // get feedback parity bit
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PUT r1 // store feedback bit to r1 temporarily
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GET r7 // get previous state again
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LSH #d1 // left shift previous state by 1
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@ -90,7 +90,7 @@ finish_preamble: LDI lfsr_routine
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JEZ r2 // jump to finish preamble loop if this plaintext == space(32)
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LDI correct_pre
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PUT r2 // put correct handler address in r2
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CHK r1 // check r1 for errors
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RXR r1 // check r1 for errors
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JEZ r2
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error_pre: LDI #x80
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STW r12
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@ -106,7 +106,7 @@ main_loop: LDI lfsr_routine // load address for the lfsr_routine label
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PUT r1 // store ciphertext in r1
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LDI correct
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PUT r2 // load address of correct handler in r2
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CHK r1 // check r1(ciphertext) for errors
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RXR r1 // check r1(ciphertext) for errors
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JEZ r2 // if there are no errors, jump to correct handler, otherwise continue to error handler
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error: LDI #x80
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STW r12
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@ -135,7 +135,8 @@ finish_post: LDI #d32
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JMP r0 // otherwise keep on padding spaces to the end
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lfsr_routine: GET r7 // get previous state
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AND r6 // and state with taps to get feedback pattern
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PTY r0 // get feedback parity bit
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CLB r0
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RXR r0 // get feedback parity bit
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PUT r1 // store feedback bit to r1 temporarily
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GET r7 // get previous state again
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LSH #d1 // left shift previous state by 1
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