From 8e6962ad4da04e2c5707fd2271167d9e011282cd Mon Sep 17 00:00:00 2001 From: Arthur Lu Date: Sat, 20 Aug 2022 01:23:00 -0700 Subject: [PATCH] combine PTY and CHK instruction, recode remaining operands --- RTL/ALU.sv | 3 +-- RTL/Ctrl.sv | 42 +++++++++++++++++++----------------------- RTL/Definitions.sv | 3 +-- firmware/assembler.py | 28 +++++++++++----------------- firmware/program1.asm | 3 ++- firmware/program2.asm | 3 ++- firmware/program3.asm | 7 ++++--- 7 files changed, 40 insertions(+), 49 deletions(-) diff --git a/RTL/ALU.sv b/RTL/ALU.sv index 8861d21..7f4450e 100644 --- a/RTL/ALU.sv +++ b/RTL/ALU.sv @@ -37,8 +37,7 @@ module ALU #(parameter W=8)( end AND: Out = A & B; // bitwise AND between A and B LSH: Out = B << A; // shift B by A bits (limitation of control) - RXOR_7: Out = ^(A[6:0]); // perform reduction XOR of lower 7 bits of A - RXOR_8: Out = ^(A[7:0]); // perform reduction XOR of lower 8 bits of A + RXOR: Out = ^(A[7:0]); // perform reduction XOR of 8 bits of A XOR: Out = A ^ B; // bitwise XOR between A and B default: Out = 'bx; // flag illegal ALU_OP values endcase diff --git a/RTL/Ctrl.sv b/RTL/Ctrl.sv index 2de87b5..e5993cb 100644 --- a/RTL/Ctrl.sv +++ b/RTL/Ctrl.sv @@ -49,26 +49,26 @@ module Ctrl #( BranchNZ = 'b0; BranchAlways = 'b0; write_mem = 'b0; - casez(Instruction[8:3]) - 'b1_????_?: begin // LDI + casez(Instruction[8:4]) + 'b1_????: begin // LDI ALU_A = I_Immediate; end - 'b0_0000_?: begin // PUT + 'b0_0000: begin // PUT Waddr = A_operand; end - 'b0_0001_?: begin // GET + 'b0_0001: begin // GET RaddrA = A_operand; end - 'b0_0010_0: begin // LDW + 'b0_0010: begin // LDW RaddrA = S_operand; RegInput = mem_out; end - 'b0_0010_1: begin // STW + 'b0_0011: begin // STW RaddrA = S_operand; RegWrite = 'b0; write_mem = 'b1; end - 'b0_0011_0: begin // NXT + 'b0_0100: begin // NXT if(S_operand == 'd8 || S_operand == 'd9 || S_operand == 'd10) begin ALU_OP = SUB; ALU_B = 'b1; @@ -81,54 +81,50 @@ module Ctrl #( RaddrA = S_operand; Waddr = S_operand; end - 'b0_0011_1: begin //CLB + 'b0_0101: begin //CLB ALU_OP = CLB; RaddrA = G_operand; Waddr = G_operand; end - 'b0_0100_?: begin // ADD + 'b0_0110: begin // ADD ALU_OP = ADD; RaddrA = A_operand; end - 'b0_0111_?: begin // AND + 'b0_0111: begin // AND ALU_OP = AND; RaddrA = A_operand; end - 'b0_1000_0: begin // LSH + 'b0_1000: begin // LSH ALU_OP = LSH; ALU_A = T_Immediate; end - 'b0_1000_1: begin // PTY - ALU_OP = RXOR_7; - RaddrA = G_operand; - end - 'b0_1001_?: begin // CHK - ALU_OP = RXOR_8; + 'b0_1001: begin // RXR + ALU_OP = RXOR; RaddrA = A_operand; end - 'b0_1010_?: begin // XOR + 'b0_1010: begin // XOR ALU_OP = XOR; RaddrA = A_operand; end - 'b0_1011_?: begin // DNE + 'b0_1011: begin // DNE Done_in = 'b1; end - 'b0_1110_0: begin // JNZ + 'b0_1100: begin // JNZ RegWrite = 'b0; RaddrA = G_operand; BranchNZ = 'b1; end - 'b0_1110_1: begin // JEZ + 'b0_1101: begin // JEZ RegWrite = 'b0; RaddrA = G_operand; BranchEZ = 'b1; end - 'b0_1111_0: begin // JMP + 'b0_1110: begin // JMP RegWrite = 'b0; RaddrA = G_operand; BranchAlways = 'b1; end - 'b0_1111_1: begin // JAL + 'b0_1111: begin // JAL RaddrA = G_operand; Waddr = 'd14; // write to link register specifically RegInput = ProgCtr_p1[7:0]; // write the value pc+4 diff --git a/RTL/Definitions.sv b/RTL/Definitions.sv index d9693de..9d60bf7 100644 --- a/RTL/Definitions.sv +++ b/RTL/Definitions.sv @@ -14,8 +14,7 @@ package Definitions; ORR, // bitwise OR AND, // bitwise AND LSH, // left shift - RXOR_7, // reduction XOR with lower 7 bits - RXOR_8, // reduction XOR with lower 8 bits + RXOR, // reduction xor XOR // bitwise XOR } op_mne; diff --git a/firmware/assembler.py b/firmware/assembler.py index 0484b48..e7a4442 100644 --- a/firmware/assembler.py +++ b/firmware/assembler.py @@ -34,12 +34,9 @@ op_type = { 'NXT': 'S', 'CLB': 'G', 'ADD': 'A', - #'SUB': 'A', - #'ORR': 'A', 'AND': 'A', 'LSH': 'T', - 'PTY': 'G', - 'CHK': 'A', + 'RXR': 'G', 'XOR': 'A', 'DNE': 'N', 'JNZ': 'G', @@ -53,22 +50,19 @@ op_codes = { 'PUT': 0b0_0000_0000, 'GET': 0b0_0001_0000, 'LDW': 0b0_0010_0000, - 'STW': 0b0_0010_1000, - 'NXT': 0b0_0011_0000, - 'CLB': 0b0_0011_1000, - 'ADD': 0b0_0100_0000, - #'SUB': 0b0_0101_0000, - #'ORR': 0b0_0110_0000, + 'STW': 0b0_0011_0000, + 'NXT': 0b0_0100_0000, + 'CLB': 0b0_0101_0000, + 'ADD': 0b0_0110_0000, 'AND': 0b0_0111_0000, 'LSH': 0b0_1000_0000, - 'PTY': 0b0_1000_1000, - 'CHK': 0b0_1001_0000, + 'RXR': 0b0_1001_0000, 'XOR': 0b0_1010_0000, - 'DNE': 0b0_1011_1111, - 'JNZ': 0b0_1110_0000, - 'JEZ': 0b0_1110_1000, - 'JMP': 0b0_1111_0000, - 'JAL': 0b0_1111_1000, + 'DNE': 0b0_1011_1111, + 'JNZ': 0b0_1100_0000, + 'JEZ': 0b0_1101_0000, + 'JMP': 0b0_1110_0000, + 'JAL': 0b0_1111_0000, 'NOP': 0b0_1000_0000 } diff --git a/firmware/program1.asm b/firmware/program1.asm index c01e50e..d4fd6f6 100644 --- a/firmware/program1.asm +++ b/firmware/program1.asm @@ -52,7 +52,8 @@ main_loop: LDW r11 // load the next plaintext byte JMP r0 // jump to main_loop if there is still space for message characters lfsr_routine: GET r7 // get previous state AND r6 // and state with taps to get feedback pattern - PTY r0 // get feedback parity bit + CLB r0 + RXR r0 // get feedback parity bit PUT r1 // store feedback bit to r1 temporarily GET r7 // get previous state again LSH #d1 // left shift previous state by 1 diff --git a/firmware/program2.asm b/firmware/program2.asm index f004521..47ef3ca 100644 --- a/firmware/program2.asm +++ b/firmware/program2.asm @@ -94,7 +94,8 @@ main_loop: LDI lfsr_routine // load address for the lfsr_routine label JMP r0 // jump to main_loop if there is still space for message characters lfsr_routine: GET r7 // get previous state AND r6 // and state with taps to get feedback pattern - PTY r0 // get feedback parity bit + CLB r0 + RXR r0 // get feedback parity bit PUT r1 // store feedback bit to r1 temporarily GET r7 // get previous state again LSH #d1 // left shift previous state by 1 diff --git a/firmware/program3.asm b/firmware/program3.asm index 891bd50..13f2eb8 100644 --- a/firmware/program3.asm +++ b/firmware/program3.asm @@ -90,7 +90,7 @@ finish_preamble: LDI lfsr_routine JEZ r2 // jump to finish preamble loop if this plaintext == space(32) LDI correct_pre PUT r2 // put correct handler address in r2 - CHK r1 // check r1 for errors + RXR r1 // check r1 for errors JEZ r2 error_pre: LDI #x80 STW r12 @@ -106,7 +106,7 @@ main_loop: LDI lfsr_routine // load address for the lfsr_routine label PUT r1 // store ciphertext in r1 LDI correct PUT r2 // load address of correct handler in r2 - CHK r1 // check r1(ciphertext) for errors + RXR r1 // check r1(ciphertext) for errors JEZ r2 // if there are no errors, jump to correct handler, otherwise continue to error handler error: LDI #x80 STW r12 @@ -135,7 +135,8 @@ finish_post: LDI #d32 JMP r0 // otherwise keep on padding spaces to the end lfsr_routine: GET r7 // get previous state AND r6 // and state with taps to get feedback pattern - PTY r0 // get feedback parity bit + CLB r0 + RXR r0 // get feedback parity bit PUT r1 // store feedback bit to r1 temporarily GET r7 // get previous state again LSH #d1 // left shift previous state by 1