Arthur Lu
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f31ac21f65
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implement ADD and SUB using CLA
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2022-08-19 23:25:31 -07:00 |
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Arthur Lu
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434032f4ba
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fix control complexity
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2022-08-19 23:16:33 -07:00 |
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Arthur Lu
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17b1b5f923
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reduction of ALU complexity by removing INC and DEC
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2022-08-19 22:44:47 -07:00 |
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Arthur Lu
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5d0f764ff5
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used block RAM for data memory
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2022-08-19 22:34:50 -07:00 |
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Arthur Lu
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c7b5b8b63c
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fix warning casez had no default
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2022-08-19 21:16:03 -07:00 |
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Arthur Lu
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550a72588d
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fix program3_tb formatting
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2022-08-19 20:24:19 -07:00 |
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Arthur Lu
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dd4f8ef9f8
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fix program 3 to have correct error detection,
added duplicate label syntax error check in assembler
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2022-08-20 03:14:36 +00:00 |
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Arthur Lu
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9254063e3e
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fix program 3 to paritally working,
add program3_tb,
fix testbench random selection
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2022-08-20 02:50:14 +00:00 |
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Arthur Lu
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36e5abab60
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fix testbench formatting
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2022-08-18 02:08:55 +00:00 |
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Arthur Lu
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570bd3698a
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fix program2
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2022-08-17 19:01:43 -07:00 |
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Arthur Lu
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9a8c9a3771
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add program2 testbench
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2022-08-17 18:01:09 -07:00 |
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Arthur Lu
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4e462c5010
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reformat program1_tb
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2022-08-15 10:48:23 -07:00 |
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Arthur Lu
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ffa7e13954
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fix file headers
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2022-08-14 16:05:44 -07:00 |
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Arthur Lu
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935864ad9c
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fix bug in PC jump target calculation,
fix bug in RegFile input width,
fix control logic bug with INC/DEC,
change assembler output format,
change programs to use d0 as space char value
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2022-08-14 13:44:51 -07:00 |
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Arthur Lu
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0dbd5dbbea
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fixed bugs in synthesis
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2022-08-13 18:54:10 -07:00 |
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Arthur Lu
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3c77111bfd
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made top_level submodule naming more verbose
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2022-08-13 18:15:45 -07:00 |
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Arthur Lu
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98fbdc5546
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populate top_level.sv
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2022-08-13 18:06:19 -07:00 |
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Arthur Lu
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ee08d3505c
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fix RegFile with correct done and start logic
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2022-08-13 17:42:57 -07:00 |
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Arthur Lu
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2839184903
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fix compile errors
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2022-08-13 17:38:45 -07:00 |
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Arthur Lu
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ed6fd943a6
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implement control comb logic (untested)
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2022-08-13 17:37:13 -07:00 |
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Arthur Lu
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2f967bef04
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push last commit
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2022-08-13 16:36:00 -07:00 |
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Arthur Lu
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be156765f3
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populate better starting rtl code
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2022-08-13 15:34:01 -07:00 |
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Arthur Lu
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31b077c5f2
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add provided RTL models
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2022-08-11 22:01:28 -07:00 |
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