Commit Graph

19 Commits

Author SHA1 Message Date
Arthur Lu
c7b5b8b63c fix warning casez had no default 2022-08-19 21:16:03 -07:00
Arthur Lu
550a72588d fix program3_tb formatting 2022-08-19 20:24:19 -07:00
Arthur Lu
dd4f8ef9f8 fix program 3 to have correct error detection,
added duplicate label syntax error check in assembler
2022-08-20 03:14:36 +00:00
Arthur Lu
9254063e3e fix program 3 to paritally working,
add program3_tb,
fix testbench random selection
2022-08-20 02:50:14 +00:00
Arthur Lu
36e5abab60 fix testbench formatting 2022-08-18 02:08:55 +00:00
Arthur Lu
570bd3698a fix program2 2022-08-17 19:01:43 -07:00
Arthur Lu
9a8c9a3771 add program2 testbench 2022-08-17 18:01:09 -07:00
Arthur Lu
4e462c5010 reformat program1_tb 2022-08-15 10:48:23 -07:00
Arthur Lu
ffa7e13954 fix file headers 2022-08-14 16:05:44 -07:00
Arthur Lu
935864ad9c fix bug in PC jump target calculation,
fix bug in RegFile input width,
fix control logic bug with INC/DEC,
change assembler output format,
change programs to use d0 as space char value
2022-08-14 13:44:51 -07:00
Arthur Lu
0dbd5dbbea fixed bugs in synthesis 2022-08-13 18:54:10 -07:00
Arthur Lu
3c77111bfd made top_level submodule naming more verbose 2022-08-13 18:15:45 -07:00
Arthur Lu
98fbdc5546 populate top_level.sv 2022-08-13 18:06:19 -07:00
Arthur Lu
ee08d3505c fix RegFile with correct done and start logic 2022-08-13 17:42:57 -07:00
Arthur Lu
2839184903 fix compile errors 2022-08-13 17:38:45 -07:00
Arthur Lu
ed6fd943a6 implement control comb logic (untested) 2022-08-13 17:37:13 -07:00
Arthur Lu
2f967bef04 push last commit 2022-08-13 16:36:00 -07:00
Arthur Lu
be156765f3 populate better starting rtl code 2022-08-13 15:34:01 -07:00
Arthur Lu
31b077c5f2 add provided RTL models 2022-08-11 22:01:28 -07:00