Arthur Lu
|
9a8c9a3771
|
add program2 testbench
|
2022-08-17 18:01:09 -07:00 |
|
Arthur Lu
|
4e462c5010
|
reformat program1_tb
|
2022-08-15 10:48:23 -07:00 |
|
Arthur Lu
|
ffa7e13954
|
fix file headers
|
2022-08-14 16:05:44 -07:00 |
|
Arthur Lu
|
935864ad9c
|
fix bug in PC jump target calculation,
fix bug in RegFile input width,
fix control logic bug with INC/DEC,
change assembler output format,
change programs to use d0 as space char value
|
2022-08-14 13:44:51 -07:00 |
|
Arthur Lu
|
0dbd5dbbea
|
fixed bugs in synthesis
|
2022-08-13 18:54:10 -07:00 |
|
Arthur Lu
|
3c77111bfd
|
made top_level submodule naming more verbose
|
2022-08-13 18:15:45 -07:00 |
|
Arthur Lu
|
98fbdc5546
|
populate top_level.sv
|
2022-08-13 18:06:19 -07:00 |
|
Arthur Lu
|
ee08d3505c
|
fix RegFile with correct done and start logic
|
2022-08-13 17:42:57 -07:00 |
|
Arthur Lu
|
2839184903
|
fix compile errors
|
2022-08-13 17:38:45 -07:00 |
|
Arthur Lu
|
ed6fd943a6
|
implement control comb logic (untested)
|
2022-08-13 17:37:13 -07:00 |
|
Arthur Lu
|
2f967bef04
|
push last commit
|
2022-08-13 16:36:00 -07:00 |
|
Arthur Lu
|
be156765f3
|
populate better starting rtl code
|
2022-08-13 15:34:01 -07:00 |
|
Arthur Lu
|
31b077c5f2
|
add provided RTL models
|
2022-08-11 22:01:28 -07:00 |
|