used block RAM for data memory

This commit is contained in:
Arthur Lu 2022-08-19 22:34:50 -07:00
parent c7b5b8b63c
commit 5d0f764ff5
2 changed files with 17 additions and 36 deletions

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@ -1,40 +1,22 @@
// Module Name: DataMem // Module Name: DataMem
// Project Name: CSE141L // Project Name: CSE141L
// control decoder (combinational, not clocked) // data memory, uses block RAM
module DataMem #(parameter W=8, A=8) ( // do not change W=8 module DataMem #(parameter W=8, A=8)(
input Clk, input logic Clk, // clock
Reset, // initialization input logic WriteEn, // '1' indicates write and '0' indicates read
WriteEn, // write enable input logic[W-1:0] DataIn, //data to be written
input [A-1:0] DataAddress, // A-bit-wide pointer to 256-deep memory input logic[A-1:0] DataAddress, //address for write or read operation
input [W-1:0] DataIn, // W-bit-wide data path, also output logic[W-1:0] DataOut //read data from memory
output logic[W-1:0] DataOut
); );
// Two dimensional memory array
// 8x256 two-dimensional array -- the memory itself logic [W-1:0] core[2**A];
logic [W-1:0] core[2**A]; logic [A-1:0] read_addr_t;
// Synchronous write
// reads are combinational always_ff@(negedge Clk) begin
always_comb if(WriteEn) core[DataAddress] <= DataIn;
DataOut = core[DataAddress]; read_addr_t = DataAddress;
end
// writes are sequential // asynchronous read
always_ff @ (posedge Clk) assign DataOut = core[read_addr_t];
/*
// Reset response is needed only for initialization.
// (see inital $readmemh above for another choice)
//
// If you do not need to preload your data memory with any constants,
// you may omit the `if (Reset) ... else` and go straight to `if(WriteEn)`
*/
if(Reset) begin
// Preload desired constants into data_mem[128:255]
//core[128] <= 'b1;
//core[129] <= 'hff;
//core[130] <= 'd64;
end
else if(WriteEn) // store
// Do the actual writes
core[DataAddress] <= DataIn;
endmodule endmodule

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@ -70,7 +70,6 @@ module top_level(
DataMem DM ( DataMem DM (
.Clk(clk), .Clk(clk),
.Reset(init),
.WriteEn(write_mem), .WriteEn(write_mem),
.DataAddress(ALU_Out), .DataAddress(ALU_Out),
.DataIn(RegOutB), .DataIn(RegOutB),