alu/cse141L-project
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Arthur Lu 5d0f764ff5 used block RAM for data memory
2022-08-19 22:34:50 -07:00
firmware
make tqdm optional,
2022-08-20 03:40:35 +00:00
RTL
used block RAM for data memory
2022-08-19 22:34:50 -07:00
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SystemVerilog 66%
Assembly 26.6%
Python 6.6%
Shell 0.5%
Dockerfile 0.3%