diff --git a/RTL/DataMem.sv b/RTL/DataMem.sv
index 3b37c5a..dfbab01 100644
--- a/RTL/DataMem.sv
+++ b/RTL/DataMem.sv
@@ -1,40 +1,22 @@
 // Module Name: DataMem
 // Project Name: CSE141L
-// control decoder (combinational, not clocked)
+// data memory, uses block RAM
 
-module DataMem #(parameter W=8, A=8) (				// do not change W=8
-  input                 Clk,
-                        Reset,		 // initialization
-                        WriteEn,	 // write enable
-  input       [A-1:0]   DataAddress, // A-bit-wide pointer to 256-deep memory
-  input       [W-1:0]   DataIn,      // W-bit-wide data path, also
-  output logic[W-1:0]   DataOut
+module DataMem #(parameter W=8, A=8)(
+	input logic Clk, // clock
+	input logic WriteEn, // '1' indicates write and '0' indicates read
+	input logic[W-1:0] DataIn, //data to be written
+	input logic[A-1:0] DataAddress, //address for write or read operation
+	output logic[W-1:0] DataOut //read data from memory
 );
-
-// 8x256 two-dimensional array -- the memory itself
-logic [W-1:0] core[2**A];
-
-// reads are combinational
-always_comb
-  DataOut = core[DataAddress];
-
-// writes are sequential
-always_ff @ (posedge Clk)
-  /*
-  // Reset response is needed only for initialization.
-  // (see inital $readmemh above for another choice)
-  //
-  // If you do not need to preload your data memory with any constants,
-  // you may omit the `if (Reset) ... else` and go straight to `if(WriteEn)`
-  */
-
-  if(Reset) begin
-    // Preload desired constants into data_mem[128:255]
-    //core[128] <= 'b1;
-  	//core[129] <= 'hff;  
-    //core[130] <= 'd64;
-  end 
-  else if(WriteEn)                    // store
-    // Do the actual writes
-    core[DataAddress] <= DataIn;
+	// Two dimensional memory array
+	logic [W-1:0] core[2**A];
+	logic [A-1:0] read_addr_t;
+	// Synchronous write
+	always_ff@(negedge Clk) begin
+		if(WriteEn) core[DataAddress] <= DataIn;
+		read_addr_t = DataAddress;
+	end
+	// asynchronous read
+	assign DataOut = core[read_addr_t];
 endmodule
diff --git a/RTL/top_level.sv b/RTL/top_level.sv
index 6d9780a..d35e926 100644
--- a/RTL/top_level.sv
+++ b/RTL/top_level.sv
@@ -70,7 +70,6 @@ module top_level(
 
 	DataMem DM (
 		.Clk(clk),
-		.Reset(init),
 		.WriteEn(write_mem),
 		.DataAddress(ALU_Out),
 		.DataIn(RegOutB),