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fix compile errors

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This commit is contained in:
Arthur Lu 2022-08-13 17:38:45 -07:00
parent ed6fd943a6
commit 2839184903
2 changed files with 3 additions and 3 deletions
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4
RTL/Ctrl.sv
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@ -69,8 +69,8 @@ module Ctrl #(
write_mem = 'b1; write_mem = 'b1;
end end
'b0_0011_0xxx: begin // NXT 'b0_0011_0xxx: begin // NXT
if(S_operand == 'd8 || S_operand == 'd9 || S_operand == d'10) ALU_OP = INC; if(S_operand == 'd8 || S_operand == 'd9 || S_operand == 'd10) ALU_OP = INC;
else if (S_operand == 'd11 || S_operand == 'd12 || S_operand == d'13) ALU_OP = DEC; else if (S_operand == 'd11 || S_operand == 'd12 || S_operand == 'd13) ALU_OP = DEC;
else ALU_OP = NOP; else ALU_OP = NOP;
RaddrA = S_operand; RaddrA = S_operand;
Waddr = S_operand; Waddr = S_operand;

2
RTL/InstFetch.sv
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@ -5,7 +5,7 @@
module InstFetch #(parameter T=10, parameter W=8)( // T is PC address size, W is the jump target pointer width, which is less module InstFetch #(parameter T=10, parameter W=8)( // T is PC address size, W is the jump target pointer width, which is less
input logic Clk, Reset, // clock, reset input logic Clk, Reset, // clock, reset
input logic BranchEZ, BranchNZ, BranchAlways, Zero, // branch control signals zero from alu signals; brnahc signals will be one hot encoding input logic BranchEZ, BranchNZ, BranchAlways, Zero, // branch control signals zero from alu signals; brnahc signals will be one hot encoding
input logic done // Done flag to indicate if the PC should increment at all input logic done, // Done flag to indicate if the PC should increment at all
input logic [W-1:0] Target, // jump target pointer input logic [W-1:0] Target, // jump target pointer
output logic [T-1:0] ProgCtr_p4 // value of pc+4 for use in JAL instruction itself output logic [T-1:0] ProgCtr_p4 // value of pc+4 for use in JAL instruction itself
); );