diff --git a/RTL/Ctrl.sv b/RTL/Ctrl.sv
index 57bf621..8c84a71 100644
--- a/RTL/Ctrl.sv
+++ b/RTL/Ctrl.sv
@@ -69,8 +69,8 @@ module Ctrl #(
 				write_mem = 'b1;
 			end
 			'b0_0011_0xxx: begin // NXT
-				if(S_operand == 'd8 || S_operand == 'd9 || S_operand == d'10) ALU_OP = INC;
-				else if (S_operand == 'd11 || S_operand == 'd12 || S_operand == d'13) ALU_OP = DEC;
+				if(S_operand == 'd8 || S_operand == 'd9 || S_operand == 'd10) ALU_OP = INC;
+				else if (S_operand == 'd11 || S_operand == 'd12 || S_operand == 'd13) ALU_OP = DEC;
 				else ALU_OP = NOP;
 				RaddrA = S_operand;
 				Waddr = S_operand;
diff --git a/RTL/InstFetch.sv b/RTL/InstFetch.sv
index 1c60605..1737b50 100644
--- a/RTL/InstFetch.sv
+++ b/RTL/InstFetch.sv
@@ -5,7 +5,7 @@
 module InstFetch #(parameter T=10, parameter W=8)(	  // T is PC address size, W is the jump target pointer width, which is less
 	input logic Clk, Reset, // clock, reset
 	input logic BranchEZ, BranchNZ, BranchAlways, Zero, // branch control signals zero from alu signals; brnahc signals will be one hot encoding
-	input logic done // Done flag to indicate if the PC should increment at all
+	input logic done, // Done flag to indicate if the PC should increment at all
 	input logic [W-1:0] Target, // jump target pointer
 	output logic [T-1:0] ProgCtr_p4 // value of pc+4 for use in JAL instruction itself
 );