17 lines
524 B
Systemverilog
17 lines
524 B
Systemverilog
//This file defines the parameters used in the alu
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// CSE141L
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// Rev. 2022.5.27
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// import package into each module that needs it
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// packages very useful for declaring global variables
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// need > 8 instructions?
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// typedef enum logic[3:0] and expand the list of enums
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package Definitions;
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// enum names will appear in timing diagram
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// ADD = 3'b000; LSH = 3'b001; etc. 3'b111 is undefined here
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typedef enum logic[2:0] {
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ADD, LSH, RSH, XOR,
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AND, SUB, CLR } op_mne;
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endpackage // definitions
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