41 lines
1.2 KiB
Systemverilog
41 lines
1.2 KiB
Systemverilog
// Module Name: ALU
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// Project Name: CSE141L
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// control decoder (combinational, not clocked)
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module DataMem #(parameter W=8, A=8) ( // do not change W=8
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input Clk,
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Reset, // initialization
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WriteEn, // write enable
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input [A-1:0] DataAddress, // A-bit-wide pointer to 256-deep memory
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input [W-1:0] DataIn, // W-bit-wide data path, also
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output logic[W-1:0] DataOut
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);
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// 8x256 two-dimensional array -- the memory itself
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logic [W-1:0] core[2**A];
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// reads are combinational
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always_comb
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DataOut = core[DataAddress];
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// writes are sequential
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always_ff @ (posedge Clk)
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/*
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// Reset response is needed only for initialization.
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// (see inital $readmemh above for another choice)
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//
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// If you do not need to preload your data memory with any constants,
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// you may omit the `if (Reset) ... else` and go straight to `if(WriteEn)`
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*/
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if(Reset) begin
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// Preload desired constants into data_mem[128:255]
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//core[128] <= 'b1;
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//core[129] <= 'hff;
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//core[130] <= 'd64;
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end
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else if(WriteEn) // store
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// Do the actual writes
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core[DataAddress] <= DataIn;
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endmodule
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