33 lines
1.0 KiB
Systemverilog
33 lines
1.0 KiB
Systemverilog
// Module Name: ALU
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// Project Name: CSE141L
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// Description: combinational (unclocked) ALU
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import Definitions::*;
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module ALU #(parameter W=8)(
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input [W-1:0] A, B, // data inputs
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input op_mne ALU_OP, // ALU opcode, part of microcode
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output logic [W-1:0] Out, // data output
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output logic Zero // zero flag
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);
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always_comb begin
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case(ALU_OP)
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NOP: Out = A; // pass A to out
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INC: Out = A + 1; // imcrement A by 1
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DEC: Out = A - 1; // decrement A by 1
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CLB: Out = {1'b0, A[6:0]}; // set MSB of A to 0
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ADD: Out = A + B; // add A to B
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SUB: Out = A - B; // subtract B from A
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ORR: Out = A | B; // bitwise OR between A and B
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AND: Out = A & B; // bitwise AND between A and B
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LSH: Out = B << A; // shift B by A bits (limitation of control)
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RXOR_7: Out = ^(A[6:0]); // perform reduction XOR of lower 7 bits of A
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RXOR_8: Out = ^(A[7:0]); // perform reduction XOR of lower 8 bits of A
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XOR: Out = A ^ B; // bitwise XOR between A and B
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default: Out = 'bx; // flag illegal ALU_OP values
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endcase
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Zero = Out == 0;
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end
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endmodule
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