141 lines
3.2 KiB
Systemverilog
141 lines
3.2 KiB
Systemverilog
// Module Name: Ctrl
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// Project Name: CSE141L
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// control decoder (combinational, not clocked)
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import Definitions::*;
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module Ctrl #(
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parameter W = 8,
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parameter T = 10
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) (
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input logic [8:0] Instruction,
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input logic [W-1:0] ALU_Out,
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input logic [W-1:0] RegOutA, RegOutB, // select from register inputs or immediate inputs
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input logic [T-1:0] ProgCtr_p1,
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input logic [W-1:0] mem_out,
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output op_mne ALU_OP, // control ALU operation
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output logic [W-1:0] ALU_A, ALU_B,
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output logic RegWrite, Done_in,
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output logic [3:0] RaddrA, RaddrB, Waddr,
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output logic [W-1:0] RegInput,
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output logic BranchEZ, BranchNZ, BranchAlways,
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output logic write_mem
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);
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logic [7:0] I_Immediate;
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logic [7:0] T_Immediate;
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logic [3:0] A_operand;
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logic [3:0] S_operand;
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logic [3:0] G_operand;
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assign I_Immediate = Instruction[7:0];
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assign T_Immediate = Instruction[2:0];
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assign A_operand = Instruction[3:0];
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assign S_operand = {1'b1, Instruction[2:0]};
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assign G_operand = {1'b0, Instruction[2:0]};
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always_comb begin
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// default values for an invalid NOP instruction, proper NOP instruction encoded as a LSH by 0
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ALU_OP = NOP;
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ALU_A = RegOutA;
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ALU_B = RegOutB;
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RegWrite = 'b1;
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Done_in = 'b0;
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RaddrA = 'b0;
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RaddrB = 'b0;
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Waddr = 'b0;
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RegInput = ALU_Out;
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BranchEZ = 'b0;
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BranchNZ = 'b0;
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BranchAlways = 'b0;
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write_mem = 'b0;
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casez(Instruction[8:4])
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'b1_????: begin // LDI
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ALU_A = I_Immediate;
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end
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'b0_0000: begin // PUT
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Waddr = A_operand;
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end
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'b0_0001: begin // GET
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RaddrA = A_operand;
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end
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'b0_0010: begin // LDW
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RaddrA = S_operand;
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RegInput = mem_out;
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end
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'b0_0011: begin // STW
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RaddrA = S_operand;
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RegWrite = 'b0;
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write_mem = 'b1;
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end
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'b0_0100: begin // NXT
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if(S_operand == 'd8 || S_operand == 'd9 || S_operand == 'd10) begin
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ALU_OP = SUB;
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ALU_B = 'b1;
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end
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else if (S_operand == 'd11 || S_operand == 'd12 || S_operand == 'd13) begin
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ALU_OP = ADD;
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ALU_B = 'b1;
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end
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else ALU_OP = NOP;
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RaddrA = S_operand;
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Waddr = S_operand;
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end
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'b0_0101: begin //CLB
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ALU_OP = CLB;
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RaddrA = G_operand;
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Waddr = G_operand;
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end
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'b0_0110: begin // ADD
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ALU_OP = ADD;
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RaddrA = A_operand;
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end
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'b0_0111: begin // AND
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ALU_OP = AND;
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RaddrA = A_operand;
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end
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'b0_1000: begin // LSH
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ALU_OP = LSH;
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ALU_A = T_Immediate;
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end
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'b0_1001: begin // RXR
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ALU_OP = RXOR;
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RaddrA = A_operand;
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end
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'b0_1010: begin // XOR
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ALU_OP = XOR;
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RaddrA = A_operand;
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end
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'b0_1011: begin // DNE
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Done_in = 'b1;
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end
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'b0_1100: begin // JNZ
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RegWrite = 'b0;
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RaddrA = G_operand;
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BranchNZ = 'b1;
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end
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'b0_1101: begin // JEZ
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RegWrite = 'b0;
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RaddrA = G_operand;
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BranchEZ = 'b1;
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end
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'b0_1110: begin // JMP
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RegWrite = 'b0;
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RaddrA = G_operand;
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BranchAlways = 'b1;
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end
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'b0_1111: begin // JAL
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RaddrA = G_operand;
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Waddr = 'd14; // write to link register specifically
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RegInput = ProgCtr_p1[7:0]; // write the value pc+4
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BranchAlways = 'b1;
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end
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default: begin
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RegWrite = 'b0;
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end
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endcase
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end
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endmodule
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