25 lines
1.2 KiB
Systemverilog
25 lines
1.2 KiB
Systemverilog
// Module Name: ALU
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// Project Name: CSE141L
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// Description: instruction fetch (pgm ctr) for processor
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module InstFetch #(parameter T=10, parameter W=8)( // T is PC address size, W is the jump target pointer width, which is less
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input logic Clk, Reset, // clock, reset
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input logic BranchEZ, BranchNZ, BranchAlways, Zero, // branch control signals zero from alu signals; brnahc signals will be one hot encoding
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input logic Done, // Done flag to indicate if the PC should increment at all
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input logic [W-1:0] Target, // jump target pointer
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output logic [T-1:0] ProgCtr,
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output logic [T-1:0] ProgCtr_p4 // value of pc+4 for use in JAL instruction itself
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);
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logic [T-1:0] PC;
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always_ff @(posedge Clk) begin
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if(Reset) PC <= 0; // if reset, set PC to 0
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else if (BranchAlways) PC <= Target; // if unconditional branch, assign PC to target
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else if (BranchEZ && Zero) PC <= Target; // if branch on zero and zero is true, then assign PC to target
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else if (BranchNZ && !Zero) PC <= Target; // if branch on non zero and zero is false, then assign PC to parget
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else if (!Done) PC <= PC + 'b1; // if not a branch but CPU is not done, then
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else PC <= PC;
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end
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endmodule |