23 lines
550 B
Systemverilog
23 lines
550 B
Systemverilog
// Module Name: ALU
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// Project Name: CSE141L
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// Description: contains enumerated ALU operations
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package Definitions;
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typedef enum logic[3:0] {
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NOP, // perform a simple value passthrough
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INC, // increment by 1
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DEC, // decrement by 1
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CLB, // clear leading bit
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ADD, // addition
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SUB, // subtraction
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ORR, // bitwise OR
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AND, // bitwise AND
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LSH, // left shift
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RXOR_7, // reduction XOR with lower 7 bits
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RXOR_8, // reduction XOR with lower 8 bits
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XOR // bitwise XOR
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} op_mne;
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endpackage // definitions
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