79 lines
1.8 KiB
Systemverilog
79 lines
1.8 KiB
Systemverilog
// Module Name: ALU
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// Project Name: CSE141L
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// Description: combinational (unclocked) ALU
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import Definitions::*;
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module ALU #(parameter W=8)(
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input [W-1:0] A, B, // data inputs
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input op_mne ALU_OP, // ALU opcode, part of microcode
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output logic [W-1:0] Out, // data output
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output logic Zero // zero flag
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);
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logic [W-1:0] AdderA, AdderB;
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logic CIN;
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logic [W:0] AdderResult;
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carry_lookahead_adder #(.N(W)) c (
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.A(AdderA),
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.B(AdderB),
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.CIN(CIN),
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.result(AdderResult)
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);
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always_comb begin
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AdderA = A;
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AdderB = B;
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CIN = 'b0;
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case(ALU_OP)
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NOP: Out = A; // pass A to out
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CLB: Out = {1'b0, A[6:0]}; // set MSB of A to 0
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ADD: Out = AdderResult[W-1:0]; // add A to B
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SUB: begin // subtract B from A
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AdderB = ~B;
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CIN = 'b1;
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Out = AdderResult[W-1:0];
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end
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AND: Out = A & B; // bitwise AND between A and B
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LSH: Out = B << A; // shift B by A bits (limitation of control)
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RXOR: Out = ^(A[7:0]); // perform reduction XOR of 8 bits of A
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XOR: Out = A ^ B; // bitwise XOR between A and B
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default: Out = 'bx; // flag illegal ALU_OP values
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endcase
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Zero = Out == 0;
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end
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endmodule
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module carry_lookahead_adder #(parameter N=16) (
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input logic[N-1:0] A, B,
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input logic CIN,
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output logic[N:0] result
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);
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logic[N-1:-1] carry;
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logic[N-1:0] p, g;
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genvar i;
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generate
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assign carry[-1] = CIN;
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for(i = 0; i < N; i++) begin : fa_loop
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fulladder f(.a(A[i]), .b(B[i]), .cin(carry[i-1]), .sum(result[i]), .cout());
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assign g[i] = A[i] & B[i];
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assign p[i] = A[i] | B[i];
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assign carry[i] = g[i] | (p[i] & carry[i-1]);
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end : fa_loop
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assign result[N] = carry[N-1];
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endgenerate
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endmodule: carry_lookahead_adder
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module fulladder(
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input logic a, b, cin,
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output logic sum, cout
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);
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logic p, q;
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assign p = a ^ b;
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assign q = a & b;
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assign sum = p ^ cin;
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assign cout = q | (p & cin);
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endmodule: fulladder |