alu/cse141L-project
Archived
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix RegFile with correct done and start logic

Browse Source
This commit is contained in:
Arthur Lu 2022-08-13 17:42:57 -07:00
parent 2839184903
commit ee08d3505c
1 changed files with 9 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
RTL/RegFile.sv
View File

@ -6,7 +6,8 @@ module RegFile #(parameter W=8, D=4)( // W = data path width (leave at 8); D =
input Clk, Reset, WriteEn, input Clk, Reset, WriteEn,
input [D-1:0] RaddrA, RaddrB, Waddr, // read anad write address pointers input [D-1:0] RaddrA, RaddrB, Waddr, // read anad write address pointers
input [W-1:0] DataIn, // data to be written input [W-1:0] DataIn, // data to be written
input Zero_in, Done_in, // since flags are stored in register file, need this as an input input logic Zero_in, Done_in, // since flags are stored in register file, need this as an input
input logic start, // start signal from testbench
output logic [W-1:0] DataOutA, DataOutB, // data to read out output logic [W-1:0] DataOutA, DataOutB, // data to read out
output logic Zero_out, Done_out // output of zero and done flags output logic Zero_out, Done_out // output of zero and done flags
); );
@ -26,8 +27,13 @@ module RegFile #(parameter W=8, D=4)( // W = data path width (leave at 8); D =
for(int i=0; i<2**D; i++) begin for(int i=0; i<2**D; i++) begin
Registers[i] <= 'h0; Registers[i] <= 'h0;
end end
Zero <= 0; Zero <= 'b0;
Done <= 1; // default Done to halt machine Done <= 'b1; // default Done to halt machine
end
else if (start) begin
Registers[Waddr] <= DataIn;
Zero <= Zero_in;
Done <= 'b0;
end end
else if (WriteEn) begin else if (WriteEn) begin
Registers[Waddr] <= DataIn; Registers[Waddr] <= DataIn;