From ee08d3505c5bca4f69c43e2a251eede6ff2e2c03 Mon Sep 17 00:00:00 2001 From: Arthur Lu Date: Sat, 13 Aug 2022 17:42:57 -0700 Subject: [PATCH] fix RegFile with correct done and start logic --- RTL/RegFile.sv | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/RTL/RegFile.sv b/RTL/RegFile.sv index 8a17c31..86d5e3f 100644 --- a/RTL/RegFile.sv +++ b/RTL/RegFile.sv @@ -6,7 +6,8 @@ module RegFile #(parameter W=8, D=4)( // W = data path width (leave at 8); D = input Clk, Reset, WriteEn, input [D-1:0] RaddrA, RaddrB, Waddr, // read anad write address pointers input [W-1:0] DataIn, // data to be written - input Zero_in, Done_in, // since flags are stored in register file, need this as an input + input logic Zero_in, Done_in, // since flags are stored in register file, need this as an input + input logic start, // start signal from testbench output logic [W-1:0] DataOutA, DataOutB, // data to read out output logic Zero_out, Done_out // output of zero and done flags ); @@ -26,8 +27,13 @@ module RegFile #(parameter W=8, D=4)( // W = data path width (leave at 8); D = for(int i=0; i<2**D; i++) begin Registers[i] <= 'h0; end - Zero <= 0; - Done <= 1; // default Done to halt machine + Zero <= 'b0; + Done <= 'b1; // default Done to halt machine + end + else if (start) begin + Registers[Waddr] <= DataIn; + Zero <= Zero_in; + Done <= 'b0; end else if (WriteEn) begin Registers[Waddr] <= DataIn;