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remove SUB instruction from ISA,

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update program2 and program3,
update control logic,
update assembler
This commit is contained in:
Arthur Lu 2022-08-19 23:34:51 -07:00
parent f31ac21f65
commit ca7bf9fc6e
4 changed files with 7 additions and 11 deletions
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6
RTL/Ctrl.sv
View File

@ -68,7 +68,7 @@ module Ctrl #(
RegWrite = 'b0; RegWrite = 'b0;
write_mem = 'b1; write_mem = 'b1;
end end
'b0_0011_0: begin // N?T 'b0_0011_0: begin // NXT
if(S_operand == 'd8 || S_operand == 'd9 || S_operand == 'd10) begin if(S_operand == 'd8 || S_operand == 'd9 || S_operand == 'd10) begin
ALU_OP = SUB; ALU_OP = SUB;
ALU_B = 'b1; ALU_B = 'b1;
@ -90,10 +90,6 @@ module Ctrl #(
ALU_OP = ADD; ALU_OP = ADD;
RaddrA = A_operand; RaddrA = A_operand;
end end
'b0_0101_?: begin // SUB
ALU_OP = SUB;
RaddrA = A_operand;
end
'b0_0110_?: begin // ORR 'b0_0110_?: begin // ORR
ALU_OP = ORR; ALU_OP = ORR;
RaddrA = A_operand; RaddrA = A_operand;

4
firmware/assembler.py
View File

@ -34,7 +34,7 @@ op_type = {
'NXT': 'S', 'NXT': 'S',
'CLB': 'G', 'CLB': 'G',
'ADD': 'A', 'ADD': 'A',
'SUB': 'A', #'SUB': 'A',
'ORR': 'A', 'ORR': 'A',
'AND': 'A', 'AND': 'A',
'LSH': 'T', 'LSH': 'T',
@ -57,7 +57,7 @@ op_codes = {
'NXT': 0b0_0011_0000, 'NXT': 0b0_0011_0000,
'CLB': 0b0_0011_1000, 'CLB': 0b0_0011_1000,
'ADD': 0b0_0100_0000, 'ADD': 0b0_0100_0000,
'SUB': 0b0_0101_0000, #'SUB': 0b0_0101_0000,
'ORR': 0b0_0110_0000, 'ORR': 0b0_0110_0000,
'AND': 0b0_0111_0000, 'AND': 0b0_0111_0000,
'LSH': 0b0_1000_0000, 'LSH': 0b0_1000_0000,

2
firmware/program2.asm
View File

@ -67,7 +67,7 @@ tap_init: LDI #d64
PUT r2 // load the outer loop top into r2 PUT r2 // load the outer loop top into r2
LDW r11 // load actual ciphertext LDW r11 // load actual ciphertext
CLB r0 // clear leading bit for r0 since we do not expect any errors for this program CLB r0 // clear leading bit for r0 since we do not expect any errors for this program
SUB r1 // subtract actual from expected, result of 0 means matching XOR r1 // XOR actual from expected, result of 0 means matching
JNZ r2 // jump to outer loop (picks new tap pattern) if the actual cipher was not equal to the expected JNZ r2 // jump to outer loop (picks new tap pattern) if the actual cipher was not equal to the expected
LDI #d32 // load preamble char LDI #d32 // load preamble char
STW r12 // store preamble char in memory STW r12 // store preamble char in memory

6
firmware/program3.asm
View File

@ -65,7 +65,7 @@ tap_init: LDI #d64
PUT r2 // load the outer loop top into r2 PUT r2 // load the outer loop top into r2
LDW r11 // load actual ciphertext LDW r11 // load actual ciphertext
CLB r0 // clear leading bit for r0 since we do not expect any errors for this program CLB r0 // clear leading bit for r0 since we do not expect any errors for this program
SUB r1 // subtract actual from expected, result of 0 means matching XOR r1 // XOR actual from expected, result of 0 means matching
JNZ r2 // jump to outer loop (picks new tap pattern) if the actual cipher was not equal to the expected JNZ r2 // jump to outer loop (picks new tap pattern) if the actual cipher was not equal to the expected
NXT r11 // increment read pointer NXT r11 // increment read pointer
NXT r9 // decrement total encryption chars remaining NXT r9 // decrement total encryption chars remaining
@ -86,7 +86,7 @@ finish_preamble: LDI lfsr_routine
LDI finish_preamble LDI finish_preamble
PUT r2 // load address of finish_preamble loop into r2 PUT r2 // load address of finish_preamble loop into r2
LDI #d32 // get value of space LDI #d32 // get value of space
SUB r1 // compare if r1 == 32 XOR r1 // compare if r1 == 32
JEZ r2 // jump to finish preamble loop if this plaintext == space(32) JEZ r2 // jump to finish preamble loop if this plaintext == space(32)
LDI correct_pre LDI correct_pre
PUT r2 // put correct handler address in r2 PUT r2 // put correct handler address in r2
@ -128,7 +128,7 @@ finish_post: LDI #d32
LDI done LDI done
PUT r1 // store done address in r1 PUT r1 // store done address in r1
LDI #d63 LDI #d63
SUB r12 // subtract r12 from 63 to see if they are equal XOR r12 // XOR r12 from 63 to see if they are equal
JEZ r1 // if write pointer == 63, then we are done JEZ r1 // if write pointer == 63, then we are done
NXT r12 // increment write pointer NXT r12 // increment write pointer
LDI finish_post LDI finish_post