From ca7bf9fc6eaa11ffa08abf6a086146518c63db46 Mon Sep 17 00:00:00 2001
From: Arthur Lu <learthurgo@gmail.com>
Date: Fri, 19 Aug 2022 23:34:51 -0700
Subject: [PATCH] remove SUB instruction from ISA, update program2 and
 program3, update control logic, update assembler

---
 RTL/Ctrl.sv           | 6 +-----
 firmware/assembler.py | 4 ++--
 firmware/program2.asm | 2 +-
 firmware/program3.asm | 6 +++---
 4 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/RTL/Ctrl.sv b/RTL/Ctrl.sv
index 792734a..3d4dcc4 100644
--- a/RTL/Ctrl.sv
+++ b/RTL/Ctrl.sv
@@ -68,7 +68,7 @@ module Ctrl #(
 				RegWrite = 'b0;
 				write_mem = 'b1;
 			end
-			'b0_0011_0: begin // N?T
+			'b0_0011_0: begin // NXT
 				if(S_operand == 'd8 || S_operand == 'd9 || S_operand == 'd10) begin
 					ALU_OP = SUB;
 					ALU_B = 'b1;
@@ -90,10 +90,6 @@ module Ctrl #(
 				ALU_OP = ADD;
 				RaddrA = A_operand;
 			end
-			'b0_0101_?: begin // SUB
-				ALU_OP = SUB;
-				RaddrA = A_operand;
-			end
 			'b0_0110_?: begin // ORR
 				ALU_OP = ORR;
 				RaddrA = A_operand;
diff --git a/firmware/assembler.py b/firmware/assembler.py
index 5521f62..2ab7f30 100644
--- a/firmware/assembler.py
+++ b/firmware/assembler.py
@@ -34,7 +34,7 @@ op_type = {
 	'NXT': 'S',
 	'CLB': 'G',
 	'ADD': 'A',
-	'SUB': 'A',
+	#'SUB': 'A',
 	'ORR': 'A',
 	'AND': 'A',
 	'LSH': 'T',
@@ -57,7 +57,7 @@ op_codes = {
 	'NXT': 0b0_0011_0000,
 	'CLB': 0b0_0011_1000,
 	'ADD': 0b0_0100_0000,
-	'SUB': 0b0_0101_0000,
+	#'SUB': 0b0_0101_0000,
 	'ORR': 0b0_0110_0000,
 	'AND': 0b0_0111_0000,
 	'LSH': 0b0_1000_0000,
diff --git a/firmware/program2.asm b/firmware/program2.asm
index 52a1bf5..db6f72b 100644
--- a/firmware/program2.asm
+++ b/firmware/program2.asm
@@ -67,7 +67,7 @@ tap_init: LDI #d64
 		PUT r2 // load the outer loop top into r2
 		LDW r11 // load actual ciphertext
 		CLB r0 // clear leading bit for r0 since we do not expect any errors for this program
-		SUB r1 // subtract actual from expected, result of 0 means matching
+		XOR r1 // XOR actual from expected, result of 0 means matching
 		JNZ r2 // jump to outer loop (picks new tap pattern) if the actual cipher was not equal to the expected
 		LDI #d32 // load preamble char
 		STW r12 // store preamble char in memory
diff --git a/firmware/program3.asm b/firmware/program3.asm
index 347d87d..d7d4d42 100644
--- a/firmware/program3.asm
+++ b/firmware/program3.asm
@@ -65,7 +65,7 @@ tap_init: LDI #d64
 		PUT r2 // load the outer loop top into r2
 		LDW r11 // load actual ciphertext
 		CLB r0 // clear leading bit for r0 since we do not expect any errors for this program
-		SUB r1 // subtract actual from expected, result of 0 means matching
+		XOR r1 // XOR actual from expected, result of 0 means matching
 		JNZ r2 // jump to outer loop (picks new tap pattern) if the actual cipher was not equal to the expected
 		NXT r11 // increment read pointer
 		NXT r9 // decrement total encryption chars remaining
@@ -86,7 +86,7 @@ finish_preamble: LDI lfsr_routine
 	LDI finish_preamble
 	PUT r2 // load address of finish_preamble loop into r2
 	LDI #d32 // get value of space
-	SUB r1 // compare if r1 == 32
+	XOR r1 // compare if r1 == 32
 	JEZ r2 // jump to finish preamble loop if this plaintext == space(32)
 	LDI correct_pre
 	PUT r2 // put correct handler address in r2
@@ -128,7 +128,7 @@ finish_post: LDI #d32
 	LDI done
 	PUT r1 // store done address in r1
 	LDI #d63
-	SUB r12 // subtract r12 from 63 to see if they are equal
+	XOR r12 // XOR r12 from 63 to see if they are equal
 	JEZ r1 // if write pointer == 63, then we are done
 	NXT r12 // increment write pointer
 	LDI finish_post