fix bug in PC jump target calculation,
fix bug in RegFile input width, fix control logic bug with INC/DEC, change assembler output format, change programs to use d0 as space char value
This commit is contained in:
Arthur Lu
parent
0dbd5dbbea
commit
935864ad9c
3
.gitignore
vendored
3
.gitignore
vendored
@ -1 +1,2 @@
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**/*.bin
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**/*.bin
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**/machine_code.txt
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51
RTL/Ctrl.sv
51
RTL/Ctrl.sv
@ -11,12 +11,13 @@ module Ctrl #(
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input logic [8:0] Instruction,
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input logic [W-1:0] ALU_Out,
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input logic [W-1:0] RegOutA, RegOutB, // select from register inputs or immediate inputs
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input logic [T-1:0] ProgCtr_p4,
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input logic [T-1:0] ProgCtr_p1,
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input logic [W-1:0] mem_out,
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output op_mne ALU_OP, // control ALU operation
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output logic [W-1:0] ALU_A, ALU_B,
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output logic RegWrite, Done_in,
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output logic [3:0] RaddrA, RaddrB, Waddr, RegInput,
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output logic [3:0] RaddrA, RaddrB, Waddr,
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output logic [W-1:0] RegInput,
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output logic BranchEZ, BranchNZ, BranchAlways,
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output logic write_mem
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);
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@ -50,90 +51,90 @@ module Ctrl #(
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BranchAlways = 'b0;
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write_mem = 'b0;
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casez(Instruction)
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'b1_xxxx_xxxx: begin // LDI
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'b1_????_????: begin // LDI
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ALU_A = I_Immediate;
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end
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'b0_0000_xxxx: begin // PUT
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'b0_0000_????: begin // PUT
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Waddr = A_operand;
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end
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'b0_0001_xxxx: begin // GET
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'b0_0001_????: begin // GET
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RaddrA = A_operand;
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end
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'b0_0010_0xxx: begin // LDW
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'b0_0010_0???: begin // LDW
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RaddrA = S_operand;
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RegInput = mem_out;
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end
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'b0_0010_1xxx: begin // STW
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'b0_0010_1???: begin // STW
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RaddrA = S_operand;
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RegWrite = 'b0;
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write_mem = 'b1;
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end
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'b0_0011_0xxx: begin // NXT
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if(S_operand == 'd8 || S_operand == 'd9 || S_operand == 'd10) ALU_OP = INC;
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else if (S_operand == 'd11 || S_operand == 'd12 || S_operand == 'd13) ALU_OP = DEC;
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'b0_0011_0???: begin // N?T
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if(S_operand == 'd8 || S_operand == 'd9 || S_operand == 'd10) ALU_OP = DEC;
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else if (S_operand == 'd11 || S_operand == 'd12 || S_operand == 'd13) ALU_OP = INC;
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else ALU_OP = NOP;
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RaddrA = S_operand;
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Waddr = S_operand;
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end
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'b0_0011_1xxx: begin //CLB
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'b0_0011_1???: begin //CLB
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ALU_OP = CLB;
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RaddrA = G_operand;
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Waddr = G_operand;
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end
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'b0_0100_xxxx: begin // ADD
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'b0_0100_????: begin // ADD
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ALU_OP = ADD;
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RaddrB = A_operand;
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end
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'b0_0101_xxxx: begin // SUB
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'b0_0101_????: begin // SUB
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ALU_OP = SUB;
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RaddrB = A_operand;
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end
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'b0_0110_xxxx: begin // ORR
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'b0_0110_????: begin // ORR
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ALU_OP = ORR;
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RaddrB = A_operand;
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end
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'b0_0111_xxxx: begin // AND
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'b0_0111_????: begin // AND
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ALU_OP = AND;
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RaddrB = A_operand;
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end
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'b0_1000_0xxx: begin // LSH
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'b0_1000_0???: begin // LSH
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ALU_OP = LSH;
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ALU_A = T_Immediate;
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end
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'b0_1000_1xxx: begin // PTY
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'b0_1000_1???: begin // PTY
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ALU_OP = RXOR_7;
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RaddrA = G_operand;
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end
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'b0_1001_xxxx: begin // CHK
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'b0_1001_????: begin // CHK
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ALU_OP = RXOR_8;
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RaddrA = A_operand;
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end
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'b0_1010_xxxx: begin // XOR
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'b0_1010_????: begin // XOR
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ALU_OP = XOR;
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RaddrB = A_operand;
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end
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'b0_1011_xxxx: begin // DNE
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'b0_1011_????: begin // DNE
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Done_in = 'b1;
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end
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'b0_1110_0xxx: begin // JNZ
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'b0_1110_0???: begin // JNZ
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RegWrite = 'b0;
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RaddrA = G_operand;
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BranchNZ = 'b1;
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end
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'b0_1110_1xxx: begin // JEZ
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'b0_1110_1???: begin // JEZ
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RegWrite = 'b0;
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RaddrA = G_operand;
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BranchEZ = 'b1;
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end
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'b0_1111_0xxx: begin // JMP
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'b0_1111_0???: begin // JMP
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RegWrite = 'b0;
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RaddrA = G_operand;
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BranchAlways = 'b1;
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end
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'b0_1111_1xxx: begin // JAL
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'b0_1111_1???: begin // JAL
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RaddrA = G_operand;
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Waddr = 'd14; // write to link register specifically
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RegInput = ProgCtr_p4; // write the value pc+4
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RegInput = ProgCtr_p1; // write the value pc+4
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BranchAlways = 'b1;
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end
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endcase
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@ -8,18 +8,21 @@ module InstFetch #(parameter T=10, parameter W=8)( // T is PC address size, W
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input logic Done, // Done flag to indicate if the PC should increment at all
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input logic [W-1:0] Target, // jump target pointer
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output logic [T-1:0] ProgCtr,
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output logic [T-1:0] ProgCtr_p4 // value of pc+4 for use in JAL instruction itself
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output logic [T-1:0] ProgCtr_p1 // value of pc+1 for use in JAL instruction itself
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);
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logic [T-1:0] PC;
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always_ff @(posedge Clk) begin
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if(Reset) PC <= 0; // if reset, set PC to 0
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else if (BranchAlways) PC <= Target; // if unconditional branch, assign PC to target
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else if (BranchEZ && Zero) PC <= Target; // if branch on zero and zero is true, then assign PC to target
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else if (BranchNZ && !Zero) PC <= Target; // if branch on non zero and zero is false, then assign PC to parget
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else if (BranchAlways) PC[W-1:0] <= Target; // if unconditional branch, assign PC to target
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else if (BranchEZ && Zero) PC[W-1:0] <= Target; // if branch on zero and zero is true, then assign PC to target
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else if (BranchNZ && !Zero) PC[W-1:0] <= Target; // if branch on non zero and zero is false, then assign PC to parget
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else if (!Done) PC <= PC + 'b1; // if not a branch but CPU is not done, then
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else PC <= PC;
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end
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assign ProgCtr = PC;
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assign ProgCtr_p1 = ProgCtr + 1;
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endmodule
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@ -10,7 +10,7 @@
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//
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// A = program counter width
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// W = machine code width -- do not change for CSE141L
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module InstROM #(parameter A=12, W=9) (
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module InstROM #(parameter A=10, W=9) (
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input [A-1:0] InstAddress,
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output logic[W-1:0] InstOut);
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@ -1,39 +1,39 @@
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// program1_tb
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// testbench for programmable message encryption (Program #1)
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// CSE141L
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// runs program 1 (encrypt a message)
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module encrypt_tb () ;
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// DUT interface -- four one-bit wires, three to DUT, one from
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// CSE141L
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// runs program 1 (encrypt a message)
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module program1_tb () ;
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// DUT interface -- four one-bit wires, three to DUT, one from
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bit clk , // advances simulation step-by-step
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init = 1'b1 , // init (reset) command to DUT
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init = 1'b1 , // init (reset) command to DUT
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start = 1'b1 ; // request (start program) command to DUT
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wire done ; // acknowledge (program done) flag returned by DUT
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// test bench parameters
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logic[7:0] pre_length ; // number of space char. before message itself, sent to data_mem[61]
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// test bench parameters
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logic[7:0] pre_length ; // number of space char. before message itself, sent to data_mem[61]
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logic[7:0] message1[54] , // original raw message, in binary, up to 54 characters in length
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msg_padded1[64], // original message, plus pre- and post-padding w/ ASCII spaces
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msg_crypto1[64]; // encrypted message returned by DUT
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logic[7:0] lfsr_ptrn , // choses one of 9 maximal length 7-tap shift reg. patterns
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LFSR_ptrn[9] , // the 9 candidate maximal-length 7-bit LFSR tap ptrns themselves
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LFSR_ptrn[9] , // the 9 candidate maximal-length 7-bit LFSR tap ptrns themselves
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lfsr1[64] , // states of program 1 encrypting LFSR
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LFSR_init ; // one of 127 possible NONZERO starting states for encrypting LFSR
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int score ; // count of correctly encyrpted characters
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int score ; // count of correctly encyrpted characters
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// our original American Standard Code for Information Interchange message follows
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// note in practice your design should be able to handle ANY ASCII string that is
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// restricted to characters between space (0x20) and script f (0x9f) and shorter than
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// note in practice your design should be able to handle ANY ASCII string that is
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// restricted to characters between space (0x20) and script f (0x9f) and shorter than
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// 55 characters in length
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string str1 = "Mr. Watson, come here. I want to see you."; // sample program 1 input
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// string str1 = " Knowledge comes, but wisdom lingers. "; // alternative inputs
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// string str1 = " 01234546789abcdefghijklmnopqrstuvwxyz. "; // (make up your own,
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// string str1 = " f A joke is a very serious thing."; // as well)
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// string str1 = " Ajoke "; //
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// string str1 = "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@";
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// string str1 = "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@";
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// string str1 = " Knowledge comes, but wisdom lingers. "; //
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// displayed encrypted string will go here:
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string str_enc1[64]; // program 1 desired output will go here
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int strlen; // length of incoming message string itself, before padding
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logic[3:0] pt_no; // select LFSR pattern, index value 0 through 8
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int strlen; // length of incoming message string itself, before padding
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logic[3:0] pt_no; // select LFSR pattern, index value 0 through 8
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int file_no; // output file tag (set to 1 for write to console/transcript)
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// the 9 possible 7-tap maximal-length feedback tap patterns from which to choose
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assign LFSR_ptrn[0] = 8'h60; // (0)110_0000
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@ -43,107 +43,107 @@ module encrypt_tb () ;
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assign LFSR_ptrn[4] = 8'h6A;
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assign LFSR_ptrn[5] = 8'h69;
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assign LFSR_ptrn[6] = 8'h5C;
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assign LFSR_ptrn[7] = 8'h7E; // (0)111_1110
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assign LFSR_ptrn[8] = 8'h7B;
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always_comb begin
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pt_no = 0;//$random; // or select a specific pattern ([0] and [1] are simplest to debug
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if(pt_no>8) pt_no[3] = 0; // restrict pt_no to 0 through 8
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assign LFSR_ptrn[7] = 8'h7E; // (0)111_1110
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assign LFSR_ptrn[8] = 8'h7B;
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always_comb begin
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pt_no = 8;//$random; // or select a specific pattern ([0] and [1] are simplest to debug
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if(pt_no>8) pt_no[3] = 0; // restrict pt_no to 0 through 8
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lfsr_ptrn = LFSR_ptrn[pt_no]; // look up and engage the selected pattern; to data_mem[62]
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end
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// now select a starting LFSR state -- any nonzero value will do
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always_comb begin
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always_comb begin
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LFSR_init = 'b1;//$random>>2; // or set a specific value, such as 7'b1, for easier debug
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if(!LFSR_init) LFSR_init = 7'b1; // prevents illegal starting state = 7'b0;
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end
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if(!LFSR_init) LFSR_init = 7'b1; // prevents illegal starting state = 7'b0;
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end
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// set preamble length for the program run (always > 9 but < 26)
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always_comb begin
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pre_length = 10;//$random>>10 ; // number of space characters ahead of message; the >>10 changes the random value
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if(pre_length < 10) pre_length = 10; // prevents pre_length < 10
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always_comb begin
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pre_length = 10;//$random>>10 ; // number of space characters ahead of message; the >>10 changes the random value
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if(pre_length < 10) pre_length = 10; // prevents pre_length < 10
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else if(pre_length > 26) pre_length = 26;
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end
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end
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// ***** instantiate your own top level design here *****
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top_level dut(
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.clk (clk ), // input: use your own port names, if different
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.init (init ), // input: some prefer to call this ".reset"
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.init (init ), // input: some prefer to call this ".reset"
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.req (start), // input: launch program
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.ack (done ) // output: "program run complete"
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);
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initial begin
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//***** pre-load your instruction ROM here or inside itself *****
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// $readmemb("encoder.bin", dut.instr_rom.rom);
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// you may also pre-load desired constants, etc. into
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// your data_mem here -- the upper addresses are reserved for your use
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initial begin
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//***** pre-load your instruction ROM here or inside itself *****
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// $readmemb("encoder.bin", dut.instr_rom.rom);
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// you may also pre-load desired constants, etc. into
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// your data_mem here -- the upper addresses are reserved for your use
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// dut.data_mem.DM[128]=8'hfe; //whatever constants you want
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// to display to console, change this line to file_no = 'b1;
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file_no = 'b1; // display to console instead of file
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// file_no = $fopen("msg_enocder_out.txt","w"); // create your output file
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// to display to console, change this line to file_no = 'b1;
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file_no = 'b1; // display to console instead of file
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// file_no = $fopen("msg_enocder_out.txt","w"); // create your output file
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#0ns strlen = str1.len; // length of string 1 (# characters between " ")
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if(strlen>54) strlen = 54; // clip message at 54 characters
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// program 1 -- precompute encrypted message
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lfsr1[0] = LFSR_init; // any nonzero value (zero may be helpful for debug)
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$fdisplay(file_no,"run encryption program; original message = ");
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$fdisplay(file_no,"%s",str1); // print original message in transcript window
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$fdisplay(file_no,"pt_no = %d",pt_no);
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$fdisplay(file_no,"pt_no = %d",pt_no);
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$fdisplay(file_no,"LFSR_ptrn = 0x%h, LFSR_init = 0x%h",lfsr_ptrn,LFSR_init);
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// will subtract 0x20 from each preamble and each message character
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// will subtract 0x20 from each preamble and each message character
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for(int j=0; j<64; j++) // pre-fill message_padded with ASCII space characters
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msg_padded1[j] = 8'h20; //
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for(int l=0; l<strlen; l++) // overwrite up to 54 of these spaces w/ message itself
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msg_padded1[pre_length+l] = str1[l]; // test bench does the -0x20 offset now
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msg_padded1[pre_length+l] = str1[l]; // test bench does the -0x20 offset now
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// compute and store the LFSR sequence
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for (int ii=0;ii<63;ii++)
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lfsr1[ii+1] = {(lfsr1[ii][5:0]),(^(lfsr1[ii]&lfsr_ptrn))};
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// encrypt the message character-by-character, then prepend the parity
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// encrypt the message character-by-character, then prepend the parity
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// testbench will change on falling clocks to avoid race conditions at rising clocks
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for (int i=0; i<64; i++) begin
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msg_crypto1[i] = ((msg_padded1[i]-32) ^ lfsr1[i]);
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msg_crypto1[i][7] = 'b0;//^msg_crypto1[i][6:0]; // prepend parity bit into MSB
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$fdisplay(file_no,"i=%d, msg_pad=0x%h, lfsr=%b msg_crypt w/ parity = 0x%h",
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i,msg_padded1[i],lfsr1[i],msg_crypto1[i]);
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msg_crypto1[i] = ((msg_padded1[i]-32) ^ lfsr1[i]);
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msg_crypto1[i][7] = 'b0;//^msg_crypto1[i][6:0]; // prepend parity bit into MSB
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$fdisplay(file_no,"i=%d, msg_pad=0x%h, lfsr=%b msg_crypt w/ parity = 0x%h",
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i,msg_padded1[i],lfsr1[i],msg_crypto1[i]);
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// for display purposes only, add 8'h20 to avoid nonprintable characters (<8'h20)
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str_enc1[i] = string'(msg_crypto1[i][6:0]+'h20);
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end
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$fdisplay(file_no,"encrypted string = ");
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$fdisplay(file_no,"encrypted string = ");
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for(int jj=0; jj<64; jj++)
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$fwrite(file_no,"%s",str_enc1[jj]);
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$fdisplay(file_no,"\n");
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// run encryption program
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// ***** load operands into your data memory *****
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// ***** use your instance name for data memory and its internal core *****
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for(int m=0; m<61; m++)
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dut.DM.core[m] = 8'h0; // pad memory w/ ASCII space characters
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// ***** load operands into your data memory *****
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// ***** use your instance name for data memory and its internal core *****
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for(int m=0; m<61; m++)
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dut.DM.core[m] = 8'h0; // pad memory w/ ASCII space characters
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for(int m=0; m<strlen; m++)
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dut.DM.core[m] = (str1[m]-8'h20); // overwrite/copy original string into device's data memory[0:strlen-1]
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dut.DM.core[61] = pre_length; // number of bytes preceding message
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dut.DM.core[62] = lfsr_ptrn; // LFSR feedback tap positions (9 permissible patterns)
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dut.DM.core[63] = LFSR_init; // LFSR starting state (nonzero)
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#20ns init = 1'b0; // suggestion: reset = 1 forces your program counter to 0
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#20ns init = 1'b0; // suggestion: reset = 1 forces your program counter to 0
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#10ns start = 1'b0; // request/start = 1 holds your program counter
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#60ns; // wait for 6 clock cycles of nominal 10ns each
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wait(done); // wait for DUT's ack/done flag to go high
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// #2000ns;
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// #2000ns;
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#10ns $fdisplay(file_no,"");
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$fdisplay(file_no,"program 1:");
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// ***** reads your results and compares to test bench
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// ***** use your instance name for data memory and its internal core *****
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// the +'h20 restores the -32 bias, for better display visuals
|
||||
for(int n=0; n<64; n++) begin
|
||||
// ***** reads your results and compares to test bench
|
||||
// ***** use your instance name for data memory and its internal core *****
|
||||
// the +'h20 restores the -32 bias, for better display visuals
|
||||
for(int n=0; n<64; n++) begin
|
||||
if(msg_crypto1[n]==dut.DM.core[n+64]) begin
|
||||
$fdisplay(file_no,"%d bench msg: %s %h dut msg: %h",
|
||||
n, msg_crypto1[n][6:0]+8'h20, msg_crypto1[n], dut.DM.core[n+64]);
|
||||
score++;
|
||||
end
|
||||
else
|
||||
$fdisplay(file_no,"%d bench msg: %s %h dut msg: %h OOPS!",
|
||||
$fdisplay(file_no,"%d bench msg: %s %h dut msg: %h",
|
||||
n, msg_crypto1[n][6:0]+8'h20, msg_crypto1[n], dut.DM.core[n+64]);
|
||||
end
|
||||
$fdisplay(file_no,"score = %d/64",score);
|
||||
score++;
|
||||
end
|
||||
else
|
||||
$fdisplay(file_no,"%d bench msg: %s %h dut msg: %h OOPS!",
|
||||
n, msg_crypto1[n][6:0]+8'h20, msg_crypto1[n], dut.DM.core[n+64]);
|
||||
end
|
||||
$fdisplay(file_no,"score = %d/64",score);
|
||||
#20ns $fclose(file_no);
|
||||
#20ns $stop;
|
||||
end
|
||||
|
||||
@ -15,12 +15,13 @@ module top_level(
|
||||
logic [8:0] Instruction;
|
||||
logic [W-1:0] ALU_Out;
|
||||
logic [W-1:0] RegOutA, RegOutB; // select from register inputs or immediate inputs
|
||||
logic [T-1:0] ProgCtr_p4;
|
||||
logic [T-1:0] ProgCtr_p1;
|
||||
logic [W-1:0] mem_out;
|
||||
op_mne ALU_OP; // control ALU operation
|
||||
logic [W-1:0] ALU_A, ALU_B;
|
||||
logic RegWrite, Done_in;
|
||||
logic [3:0] RaddrA, RaddrB, Waddr, RegInput;
|
||||
logic [3:0] RaddrA, RaddrB, Waddr;
|
||||
logic [W-1:0] RegInput;
|
||||
logic BranchEZ, BranchNZ, BranchAlways;
|
||||
logic write_mem;
|
||||
logic Zero_in, Zero_out;
|
||||
@ -47,7 +48,7 @@ module top_level(
|
||||
.Done(Done_out),
|
||||
.Target(ALU_A),
|
||||
.ProgCtr(ProgCtr),
|
||||
.ProgCtr_p4(ProgCtr_p4)
|
||||
.ProgCtr_p1(ProgCtr_p1)
|
||||
);
|
||||
|
||||
RegFile regfile (
|
||||
@ -67,7 +68,7 @@ module top_level(
|
||||
.Done_out(Done_out)
|
||||
);
|
||||
|
||||
DataMem datamem (
|
||||
DataMem DM (
|
||||
.Clk(clk),
|
||||
.Reset(init),
|
||||
.WriteEn(write_mem),
|
||||
|
||||
@ -99,7 +99,8 @@ def get_immediate(operand, labels):
|
||||
|
||||
output = sys.argv[1]
|
||||
targets = sys.argv[2:]
|
||||
out = open(output, "wb")
|
||||
#out = open(output, "wb")
|
||||
out = open(output, "w")
|
||||
print('detected targets: ' + str(targets))
|
||||
for file in targets:
|
||||
print('assembing: ' + file)
|
||||
@ -139,4 +140,5 @@ for file in targets:
|
||||
for inst in tqdm(instructions, desc='Assembly', unit=' instructions'):
|
||||
opcode = op_codes[inst[0]]
|
||||
operand = inst[1]
|
||||
out.write((opcode| operand).to_bytes(length=2, byteorder='big'))
|
||||
out.write(format(opcode | operand, 'b') + '\n')
|
||||
#out.write((opcode| operand).to_bytes(length=2, byteorder='big'))
|
||||
@ -1,2 +1,2 @@
|
||||
#!/bin/sh
|
||||
python assembler.py cse141L.bin program1.asm program2.asm program3.asm
|
||||
python assembler.py machine_code.txt program1.asm program2.asm program3.asm
|
||||
@ -24,7 +24,7 @@ init: LDI #d62
|
||||
PUT r8 // init r8 decrementer with number of preamble space chars
|
||||
LDI #d64
|
||||
PUT r9 // init r9 decrementer to total number of possible ciphertext chars
|
||||
preamble_loop: LDI #d32 // get space character decimal 32
|
||||
preamble_loop: LDI #d0 // get space character decimal 0
|
||||
XOR r7 // bitwise XOR the current state with plaintext space to generate ciphertext
|
||||
CLB r0 // clear the leading bit of the ciphertext as in requirements
|
||||
STW r12 // store ciphertext to write pointer
|
||||
|
||||
@ -59,7 +59,7 @@ tap_init: LDI #d64
|
||||
NXT r9 // decrement total encryption chars remaining
|
||||
tap_loop: LDI lfsr_routine
|
||||
JAL r0 // jump to lfsr routine which calculates next state in r7
|
||||
LDI #d32 // load space char expected plaintext
|
||||
LDI #d0 // load space char expected plaintext
|
||||
XOR r7
|
||||
CLB r0 // clear leading bit in the expected ciphertext
|
||||
PUT r1 // store expected cipher text in r1
|
||||
|
||||
@ -59,7 +59,7 @@ tap_init: LDI #d64
|
||||
NXT r9 // decrement total encryption chars remaining
|
||||
tap_loop: LDI lfsr_routine
|
||||
JAL r0 // jump to lfsr routine which calculates next state in r7
|
||||
LDI #d32 // load space char expected plaintext
|
||||
LDI #d0 // load space char expected plaintext
|
||||
XOR r7
|
||||
CLB r0 // clear leading bit in the expected ciphertext
|
||||
PUT r1 // store expected cipher text in r1
|
||||
|
||||
Reference in New Issue
Block a user