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fix bug in PC jump target calculation,

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fix bug in RegFile input width,
fix control logic bug with INC/DEC,
change assembler output format,
change programs to use d0 as space char value
This commit is contained in:
Arthur Lu 2022-08-14 13:44:51 -07:00
parent 0dbd5dbbea
commit 935864ad9c
11 changed files with 113 additions and 105 deletions
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1
.gitignore vendored
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@ -1 +1,2 @@
**/*.bin **/*.bin
**/machine_code.txt

51
RTL/Ctrl.sv
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@ -11,12 +11,13 @@ module Ctrl #(
input logic [8:0] Instruction, input logic [8:0] Instruction,
input logic [W-1:0] ALU_Out, input logic [W-1:0] ALU_Out,
input logic [W-1:0] RegOutA, RegOutB, // select from register inputs or immediate inputs input logic [W-1:0] RegOutA, RegOutB, // select from register inputs or immediate inputs
input logic [T-1:0] ProgCtr_p4, input logic [T-1:0] ProgCtr_p1,
input logic [W-1:0] mem_out, input logic [W-1:0] mem_out,
output op_mne ALU_OP, // control ALU operation output op_mne ALU_OP, // control ALU operation
output logic [W-1:0] ALU_A, ALU_B, output logic [W-1:0] ALU_A, ALU_B,
output logic RegWrite, Done_in, output logic RegWrite, Done_in,
output logic [3:0] RaddrA, RaddrB, Waddr, RegInput, output logic [3:0] RaddrA, RaddrB, Waddr,
output logic [W-1:0] RegInput,
output logic BranchEZ, BranchNZ, BranchAlways, output logic BranchEZ, BranchNZ, BranchAlways,
output logic write_mem output logic write_mem
); );
@ -50,90 +51,90 @@ module Ctrl #(
BranchAlways = 'b0; BranchAlways = 'b0;
write_mem = 'b0; write_mem = 'b0;
casez(Instruction) casez(Instruction)
'b1_xxxx_xxxx: begin // LDI 'b1_????_????: begin // LDI
ALU_A = I_Immediate; ALU_A = I_Immediate;
end end
'b0_0000_xxxx: begin // PUT 'b0_0000_????: begin // PUT
Waddr = A_operand; Waddr = A_operand;
end end
'b0_0001_xxxx: begin // GET 'b0_0001_????: begin // GET
RaddrA = A_operand; RaddrA = A_operand;
end end
'b0_0010_0xxx: begin // LDW 'b0_0010_0???: begin // LDW
RaddrA = S_operand; RaddrA = S_operand;
RegInput = mem_out; RegInput = mem_out;
end end
'b0_0010_1xxx: begin // STW 'b0_0010_1???: begin // STW
RaddrA = S_operand; RaddrA = S_operand;
RegWrite = 'b0; RegWrite = 'b0;
write_mem = 'b1; write_mem = 'b1;
end end
'b0_0011_0xxx: begin // NXT 'b0_0011_0???: begin // N?T
if(S_operand == 'd8 || S_operand == 'd9 || S_operand == 'd10) ALU_OP = INC; if(S_operand == 'd8 || S_operand == 'd9 || S_operand == 'd10) ALU_OP = DEC;
else if (S_operand == 'd11 || S_operand == 'd12 || S_operand == 'd13) ALU_OP = DEC; else if (S_operand == 'd11 || S_operand == 'd12 || S_operand == 'd13) ALU_OP = INC;
else ALU_OP = NOP; else ALU_OP = NOP;
RaddrA = S_operand; RaddrA = S_operand;
Waddr = S_operand; Waddr = S_operand;
end end
'b0_0011_1xxx: begin //CLB 'b0_0011_1???: begin //CLB
ALU_OP = CLB; ALU_OP = CLB;
RaddrA = G_operand; RaddrA = G_operand;
Waddr = G_operand; Waddr = G_operand;
end end
'b0_0100_xxxx: begin // ADD 'b0_0100_????: begin // ADD
ALU_OP = ADD; ALU_OP = ADD;
RaddrB = A_operand; RaddrB = A_operand;
end end
'b0_0101_xxxx: begin // SUB 'b0_0101_????: begin // SUB
ALU_OP = SUB; ALU_OP = SUB;
RaddrB = A_operand; RaddrB = A_operand;
end end
'b0_0110_xxxx: begin // ORR 'b0_0110_????: begin // ORR
ALU_OP = ORR; ALU_OP = ORR;
RaddrB = A_operand; RaddrB = A_operand;
end end
'b0_0111_xxxx: begin // AND 'b0_0111_????: begin // AND
ALU_OP = AND; ALU_OP = AND;
RaddrB = A_operand; RaddrB = A_operand;
end end
'b0_1000_0xxx: begin // LSH 'b0_1000_0???: begin // LSH
ALU_OP = LSH; ALU_OP = LSH;
ALU_A = T_Immediate; ALU_A = T_Immediate;
end end
'b0_1000_1xxx: begin // PTY 'b0_1000_1???: begin // PTY
ALU_OP = RXOR_7; ALU_OP = RXOR_7;
RaddrA = G_operand; RaddrA = G_operand;
end end
'b0_1001_xxxx: begin // CHK 'b0_1001_????: begin // CHK
ALU_OP = RXOR_8; ALU_OP = RXOR_8;
RaddrA = A_operand; RaddrA = A_operand;
end end
'b0_1010_xxxx: begin // XOR 'b0_1010_????: begin // XOR
ALU_OP = XOR; ALU_OP = XOR;
RaddrB = A_operand; RaddrB = A_operand;
end end
'b0_1011_xxxx: begin // DNE 'b0_1011_????: begin // DNE
Done_in = 'b1; Done_in = 'b1;
end end
'b0_1110_0xxx: begin // JNZ 'b0_1110_0???: begin // JNZ
RegWrite = 'b0; RegWrite = 'b0;
RaddrA = G_operand; RaddrA = G_operand;
BranchNZ = 'b1; BranchNZ = 'b1;
end end
'b0_1110_1xxx: begin // JEZ 'b0_1110_1???: begin // JEZ
RegWrite = 'b0; RegWrite = 'b0;
RaddrA = G_operand; RaddrA = G_operand;
BranchEZ = 'b1; BranchEZ = 'b1;
end end
'b0_1111_0xxx: begin // JMP 'b0_1111_0???: begin // JMP
RegWrite = 'b0; RegWrite = 'b0;
RaddrA = G_operand; RaddrA = G_operand;
BranchAlways = 'b1; BranchAlways = 'b1;
end end
'b0_1111_1xxx: begin // JAL 'b0_1111_1???: begin // JAL
RaddrA = G_operand; RaddrA = G_operand;
Waddr = 'd14; // write to link register specifically Waddr = 'd14; // write to link register specifically
RegInput = ProgCtr_p4; // write the value pc+4 RegInput = ProgCtr_p1; // write the value pc+4
BranchAlways = 'b1; BranchAlways = 'b1;
end end
endcase endcase

11
RTL/InstFetch.sv
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@ -8,18 +8,21 @@ module InstFetch #(parameter T=10, parameter W=8)( // T is PC address size, W
input logic Done, // Done flag to indicate if the PC should increment at all input logic Done, // Done flag to indicate if the PC should increment at all
input logic [W-1:0] Target, // jump target pointer input logic [W-1:0] Target, // jump target pointer
output logic [T-1:0] ProgCtr, output logic [T-1:0] ProgCtr,
output logic [T-1:0] ProgCtr_p4 // value of pc+4 for use in JAL instruction itself output logic [T-1:0] ProgCtr_p1 // value of pc+1 for use in JAL instruction itself
); );
logic [T-1:0] PC; logic [T-1:0] PC;
always_ff @(posedge Clk) begin always_ff @(posedge Clk) begin
if(Reset) PC <= 0; // if reset, set PC to 0 if(Reset) PC <= 0; // if reset, set PC to 0
else if (BranchAlways) PC <= Target; // if unconditional branch, assign PC to target else if (BranchAlways) PC[W-1:0] <= Target; // if unconditional branch, assign PC to target
else if (BranchEZ && Zero) PC <= Target; // if branch on zero and zero is true, then assign PC to target else if (BranchEZ && Zero) PC[W-1:0] <= Target; // if branch on zero and zero is true, then assign PC to target
else if (BranchNZ && !Zero) PC <= Target; // if branch on non zero and zero is false, then assign PC to parget else if (BranchNZ && !Zero) PC[W-1:0] <= Target; // if branch on non zero and zero is false, then assign PC to parget
else if (!Done) PC <= PC + 'b1; // if not a branch but CPU is not done, then else if (!Done) PC <= PC + 'b1; // if not a branch but CPU is not done, then
else PC <= PC; else PC <= PC;
end end
assign ProgCtr = PC;
assign ProgCtr_p1 = ProgCtr + 1;
endmodule endmodule

2
RTL/InstROM.sv
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@ -10,7 +10,7 @@
// //
// A = program counter width // A = program counter width
// W = machine code width -- do not change for CSE141L // W = machine code width -- do not change for CSE141L
module InstROM #(parameter A=12, W=9) ( module InstROM #(parameter A=10, W=9) (
input [A-1:0] InstAddress, input [A-1:0] InstAddress,
output logic[W-1:0] InstOut); output logic[W-1:0] InstOut);

4
RTL/program1_tb1.sv
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@ -2,7 +2,7 @@
// testbench for programmable message encryption (Program #1) // testbench for programmable message encryption (Program #1)
// CSE141L // CSE141L
// runs program 1 (encrypt a message) // runs program 1 (encrypt a message)
module encrypt_tb () ; module program1_tb () ;
// DUT interface -- four one-bit wires, three to DUT, one from // DUT interface -- four one-bit wires, three to DUT, one from
bit clk , // advances simulation step-by-step bit clk , // advances simulation step-by-step
init = 1'b1 , // init (reset) command to DUT init = 1'b1 , // init (reset) command to DUT
@ -46,7 +46,7 @@ module encrypt_tb () ;
assign LFSR_ptrn[7] = 8'h7E; // (0)111_1110 assign LFSR_ptrn[7] = 8'h7E; // (0)111_1110
assign LFSR_ptrn[8] = 8'h7B; assign LFSR_ptrn[8] = 8'h7B;
always_comb begin always_comb begin
pt_no = 0;//$random; // or select a specific pattern ([0] and [1] are simplest to debug pt_no = 8;//$random; // or select a specific pattern ([0] and [1] are simplest to debug
if(pt_no>8) pt_no[3] = 0; // restrict pt_no to 0 through 8 if(pt_no>8) pt_no[3] = 0; // restrict pt_no to 0 through 8
lfsr_ptrn = LFSR_ptrn[pt_no]; // look up and engage the selected pattern; to data_mem[62] lfsr_ptrn = LFSR_ptrn[pt_no]; // look up and engage the selected pattern; to data_mem[62]
end end

9
RTL/top_level.sv
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@ -15,12 +15,13 @@ module top_level(
logic [8:0] Instruction; logic [8:0] Instruction;
logic [W-1:0] ALU_Out; logic [W-1:0] ALU_Out;
logic [W-1:0] RegOutA, RegOutB; // select from register inputs or immediate inputs logic [W-1:0] RegOutA, RegOutB; // select from register inputs or immediate inputs
logic [T-1:0] ProgCtr_p4; logic [T-1:0] ProgCtr_p1;
logic [W-1:0] mem_out; logic [W-1:0] mem_out;
op_mne ALU_OP; // control ALU operation op_mne ALU_OP; // control ALU operation
logic [W-1:0] ALU_A, ALU_B; logic [W-1:0] ALU_A, ALU_B;
logic RegWrite, Done_in; logic RegWrite, Done_in;
logic [3:0] RaddrA, RaddrB, Waddr, RegInput; logic [3:0] RaddrA, RaddrB, Waddr;
logic [W-1:0] RegInput;
logic BranchEZ, BranchNZ, BranchAlways; logic BranchEZ, BranchNZ, BranchAlways;
logic write_mem; logic write_mem;
logic Zero_in, Zero_out; logic Zero_in, Zero_out;
@ -47,7 +48,7 @@ module top_level(
.Done(Done_out), .Done(Done_out),
.Target(ALU_A), .Target(ALU_A),
.ProgCtr(ProgCtr), .ProgCtr(ProgCtr),
.ProgCtr_p4(ProgCtr_p4) .ProgCtr_p1(ProgCtr_p1)
); );
RegFile regfile ( RegFile regfile (
@ -67,7 +68,7 @@ module top_level(
.Done_out(Done_out) .Done_out(Done_out)
); );
DataMem datamem ( DataMem DM (
.Clk(clk), .Clk(clk),
.Reset(init), .Reset(init),
.WriteEn(write_mem), .WriteEn(write_mem),

6
firmware/assembler.py
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@ -99,7 +99,8 @@ def get_immediate(operand, labels):
output = sys.argv[1] output = sys.argv[1]
targets = sys.argv[2:] targets = sys.argv[2:]
out = open(output, "wb") #out = open(output, "wb")
out = open(output, "w")
print('detected targets: ' + str(targets)) print('detected targets: ' + str(targets))
for file in targets: for file in targets:
print('assembing: ' + file) print('assembing: ' + file)
@ -139,4 +140,5 @@ for file in targets:
for inst in tqdm(instructions, desc='Assembly', unit=' instructions'): for inst in tqdm(instructions, desc='Assembly', unit=' instructions'):
opcode = op_codes[inst[0]] opcode = op_codes[inst[0]]
operand = inst[1] operand = inst[1]
out.write((opcode| operand).to_bytes(length=2, byteorder='big')) out.write(format(opcode | operand, 'b') + '\n')
#out.write((opcode| operand).to_bytes(length=2, byteorder='big'))

2
firmware/example.sh
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@ -1,2 +1,2 @@
#!/bin/sh #!/bin/sh
python assembler.py cse141L.bin program1.asm program2.asm program3.asm python assembler.py machine_code.txt program1.asm program2.asm program3.asm

2
firmware/program1.asm
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@ -24,7 +24,7 @@ init: LDI #d62
PUT r8 // init r8 decrementer with number of preamble space chars PUT r8 // init r8 decrementer with number of preamble space chars
LDI #d64 LDI #d64
PUT r9 // init r9 decrementer to total number of possible ciphertext chars PUT r9 // init r9 decrementer to total number of possible ciphertext chars
preamble_loop: LDI #d32 // get space character decimal 32 preamble_loop: LDI #d0 // get space character decimal 0
XOR r7 // bitwise XOR the current state with plaintext space to generate ciphertext XOR r7 // bitwise XOR the current state with plaintext space to generate ciphertext
CLB r0 // clear the leading bit of the ciphertext as in requirements CLB r0 // clear the leading bit of the ciphertext as in requirements
STW r12 // store ciphertext to write pointer STW r12 // store ciphertext to write pointer

2
firmware/program2.asm
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@ -59,7 +59,7 @@ tap_init: LDI #d64
NXT r9 // decrement total encryption chars remaining NXT r9 // decrement total encryption chars remaining
tap_loop: LDI lfsr_routine tap_loop: LDI lfsr_routine
JAL r0 // jump to lfsr routine which calculates next state in r7 JAL r0 // jump to lfsr routine which calculates next state in r7
LDI #d32 // load space char expected plaintext LDI #d0 // load space char expected plaintext
XOR r7 XOR r7
CLB r0 // clear leading bit in the expected ciphertext CLB r0 // clear leading bit in the expected ciphertext
PUT r1 // store expected cipher text in r1 PUT r1 // store expected cipher text in r1

2
firmware/program3.asm
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@ -59,7 +59,7 @@ tap_init: LDI #d64
NXT r9 // decrement total encryption chars remaining NXT r9 // decrement total encryption chars remaining
tap_loop: LDI lfsr_routine tap_loop: LDI lfsr_routine
JAL r0 // jump to lfsr routine which calculates next state in r7 JAL r0 // jump to lfsr routine which calculates next state in r7
LDI #d32 // load space char expected plaintext LDI #d0 // load space char expected plaintext
XOR r7 XOR r7
CLB r0 // clear leading bit in the expected ciphertext CLB r0 // clear leading bit in the expected ciphertext
PUT r1 // store expected cipher text in r1 PUT r1 // store expected cipher text in r1