47 lines
1.9 KiB
Systemverilog
47 lines
1.9 KiB
Systemverilog
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// Create Date: 2019.01.25
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// Design Name: CSE141L
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// Module Name: reg_file
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// Revision: 2022.05.04
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// Additional Comments: allows preloading with user constants
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// This version is fully synthesizable and highly recommended.
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/* parameters are compile time directives
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this can be an any-width, any-depth reg_file: just override the params!
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*/
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module RegFile #(parameter W=8, D=4)( // W = data path width (leave at 8); D = address pointer width
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input Clk,
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Reset, // note use of Reset port
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WriteEn,
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input [D-1:0] RaddrA, // address pointers
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RaddrB,
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Waddr,
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input [W-1:0] DataIn,
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output [W-1:0] DataOutA, // showing two different ways to handle DataOutX, for
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output logic [W-1:0] DataOutB // pedagogic reasons only
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);
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// W bits wide [W-1:0] and 2**4 registers deep
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logic [W-1:0] Registers[2**D]; // or just registers[16] if we know D=4 always
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// combinational reads
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/* can use always_comb in place of assign
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difference: assign is limited to one line of code, so
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always_comb is much more versatile
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*/
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assign DataOutA = Registers[RaddrA]; // assign & always_comb do the same thing here
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always_comb DataOutB = Registers[RaddrB]; // can read from addr 0, just like ARM
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// sequential (clocked) writes
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always_ff @ (posedge Clk)
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if (Reset) begin
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for(int i=0; i<2**D; i++)
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Registers[i] <= 'h0;
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// we can override this universal clear command with desired initialization values
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Registers[0] <= 'd30; // loads 30 (=0x1E) into RegFile address 0
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Registers[2] <= 'b101; // loads 00000101 into RegFile address 2
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end
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else if (WriteEn) // works just like data_memory writes
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Registers[Waddr] <= DataIn;
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endmodule
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