32 lines
797 B
Systemverilog
32 lines
797 B
Systemverilog
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module InstFetch_TB();
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logic Reset = 1'b1,
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Start = 1'b0,
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Clk = 1'b0,
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BranchAbs = 1'b0,
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BranchRelEn = 1'b0,
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ALU_flag = 1'b0;
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logic [9:0] Target = 'b1; //10'h3fc;//'1; -4
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wire [9:0] ProgCtr;
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InstFetch IF1(.*);
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always begin
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#5ns Clk = 1'b1;
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#5ns Clk = 1'b0;
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end
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initial begin
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#20ns Reset = 1'b0;
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#20ns Start = 1'b1;
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#20ns Start = 1'b0;
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#120ns BranchAbs = 1'b1; // should reset PC to 0
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#30ns BranchAbs = 1'b0;
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#250ns BranchRelEn = 1'b1;
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Target = 'h3fc; // -4
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#20ns ALU_flag = 1'b1;
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#40ns ALU_flag = 1'b0;
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#240ns $stop;
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end
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endmodule
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