38 lines
2.0 KiB
Systemverilog
38 lines
2.0 KiB
Systemverilog
// Design Name: basic_proc
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// Module Name: InstFetch
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// Project Name: CSE141L
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// Description: instruction fetch (pgm ctr) for processor
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//
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// Revision: 2021.11.27
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// Suggested ProgCtr width 10 t0 12 bits
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module InstFetch #(parameter T=10)( // PC width -- up to 32, if you like
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input Reset, // reset, init, etc. -- force PC to 0
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Start, // begin next program in series (request issued by test bench)
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Clk, // PC can change on pos. edges only
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BranchAbs, // jump conditionally to Target value
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BranchRelEn, // jump conditionally to Target + PC
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ALU_flag, // flag from ALU, e.g. Zero, Carry, Overflow, Negative (from ARM)
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input [T-1:0] Target, // jump ... "how high?"
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output logic [T-1:0] ProgCtr // the program counter register itself
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);
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// you may wish to use either absolute or relative branching
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// you may use both, but you will need appropriate control bits
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// branch/jump is how we handle gosub and return to main
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// program counter can clear to 0, increment, or branch
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// for unconditional branching, "ALU_flag" input should be driven by 1
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always_ff @(posedge Clk) // or just always; always_ff is a linting construct
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if(Reset)
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ProgCtr <= 0; // for first program; want different value for 2nd or 3rd
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else if(Start) // hold while start asserted; commence when released
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ProgCtr <= 0; //or <= ProgCtr; holds at starting value
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else if(BranchAbs && ALU_flag // unconditional absolute jump
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ProgCtr <= Target; // how would you make it conditional and/or relative?
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else if(BranchRelEn && ALU_flag) // conditional relative jump
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ProgCtr <= Target + ProgCtr; // how would you make it unconditional and/or absolute
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else
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ProgCtr <= ProgCtr+'b1; // default increment (no need for ARM/MIPS +4 -- why?)
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endmodule
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