47 lines
1.9 KiB
Systemverilog
47 lines
1.9 KiB
Systemverilog
// Module Name: ALU
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// Project Name: CSE141L
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//
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// Additional Comments:
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// combinational (unclocked) ALU
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// includes package "Definitions"
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// be sure to adjust "Definitions" to match your final set of ALU opcodes
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import Definitions::*;
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module ALU #(parameter W=8)(
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input [W-1:0] InputA, // data inputs
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InputB,
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input op_mne OP, // ALU opcode, part of microcode
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input SC_in, // shift or carry in
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output logic [W-1:0] Out, // data output
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output logic Zero, // output = zero flag !(Out)
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Parity, // outparity flag ^(Out)
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Odd, // output odd flag (Out[0])
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SC_out // shift or carry out
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// you may provide additional status flags, if desired
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// comment out or delete any you don't need
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);
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always_comb begin
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// No Op = default
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// add desired ALU ops, delete or comment out any you don't need
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Out = 8'b0; // don't need NOOP? Out = 8'bx
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SC_out = 1'b0; // will flag any illegal opcodes
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case(OP)
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ADD : {SC_out,Out} = InputA + InputB + SC_in; // unsigned add with carry-in and carry-out
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LSH : {SC_out,Out} = {InputA[7:0],SC_in}; // shift left, fill in with SC_in, fill SC_out with InputA[7]
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// for logical left shift, tie SC_in = 0
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RSH : {Out,SC_out} = {SC_in, InputA[7:0]}; // shift right
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XOR : Out = InputA ^ InputB; // bitwise exclusive OR
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AND : Out = InputA & InputB; // bitwise AND
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SUB : {SC_out,Out} = InputA + (~InputB) + 1; // InputA - InputB;
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CLR : {SC_out,Out} = 'b0;
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endcase
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end
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assign Zero = ~|Out; // reduction NOR Zero = !Out;
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assign Parity = ^Out; // reduction XOR
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assign Odd = Out[0]; // odd/even -- just the value of the LSB
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endmodule
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