23 lines
677 B
Systemverilog
23 lines
677 B
Systemverilog
// Module Name: DataMem
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// Project Name: CSE141L
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// data memory, uses block RAM
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module DataMem #(parameter W=8, A=8)(
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input logic Clk, // clock
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input logic WriteEn, // '1' indicates write and '0' indicates read
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input logic[W-1:0] DataIn, //data to be written
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input logic[A-1:0] DataAddress, //address for write or read operation
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output logic[W-1:0] DataOut //read data from memory
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);
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// Two dimensional memory array
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logic [W-1:0] core[2**A];
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logic [A-1:0] read_addr_t;
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// Synchronous write
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always_ff@(negedge Clk) begin
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if(WriteEn) core[DataAddress] <= DataIn;
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read_addr_t = DataAddress;
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end
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// asynchronous read
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assign DataOut = core[read_addr_t];
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endmodule
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