88 lines
1.6 KiB
Systemverilog
88 lines
1.6 KiB
Systemverilog
// Module Name: top_level
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// Project Name: CSE141L
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// Description: top level RTL for processor
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import Definitions::*;
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module top_level(
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input clk, init, req,
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output logic ack
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);
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parameter T=10;
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parameter W=8;
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logic [8:0] Instruction;
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logic [W-1:0] ALU_Out;
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logic [W-1:0] RegOutA, RegOutB; // select from register inputs or immediate inputs
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logic [T-1:0] ProgCtr_p1;
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logic [W-1:0] mem_out;
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op_mne ALU_OP; // control ALU operation
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logic [W-1:0] ALU_A, ALU_B;
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logic RegWrite, Done_in;
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logic [3:0] RaddrA, RaddrB, Waddr;
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logic [W-1:0] RegInput;
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logic BranchEZ, BranchNZ, BranchAlways;
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logic write_mem;
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logic Zero_in, Zero_out;
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logic Done_out;
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logic [T-1:0] ProgCtr;
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Ctrl control (.*);
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ALU alu (
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.A(ALU_A),
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.B(ALU_B),
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.ALU_OP(ALU_OP),
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.Out(ALU_Out),
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.Zero(Zero_in)
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);
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InstFetch pc (
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.Clk(clk),
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.Reset(init),
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.BranchEZ(BranchEZ),
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.BranchNZ(BranchNZ),
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.BranchAlways(BranchAlways),
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.Zero(Zero_out),
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.Done(Done_out),
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.Target(ALU_A),
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.ProgCtr(ProgCtr),
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.ProgCtr_p1(ProgCtr_p1)
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);
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RegFile regfile (
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.Clk(clk),
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.Reset(init),
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.WriteEn(RegWrite),
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.RaddrA(RaddrA),
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.RaddrB(RaddrB),
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.Waddr(Waddr),
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.DataIn(RegInput),
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.Zero_in(Zero_in),
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.Done_in(Done_in),
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.start(req),
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.DataOutA(RegOutA),
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.DataOutB(RegOutB),
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.Zero_out(Zero_out),
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.Done_out(Done_out)
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);
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DataMem DM (
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.Clk(clk),
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.WriteEn(write_mem),
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.DataAddress(ALU_Out),
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.DataIn(RegOutB),
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.DataOut(mem_out)
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);
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InstROM rom (
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.InstAddress(ProgCtr),
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.InstOut(Instruction)
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);
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assign ack = Done_out;
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endmodule
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