35 lines
959 B
Systemverilog
35 lines
959 B
Systemverilog
// Module Name: RegFile
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// Project Name: CSE141L
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// Description: register file
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module RegFile #(parameter W=8, D=4)( // W = data path width (leave at 8); D = address pointer width
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input logic Clk, Reset, WriteEn,
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input logic [D-1:0] RaddrA, RaddrB, Waddr, // read anad write address pointers
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input logic [W-1:0] DataIn, // data to be written
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input logic start, // start signal from testbench
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output logic [W-1:0] DataOutA, DataOutB // data to read out
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);
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logic [W-1:0] Registers[2**D]; // 2^D registers of with W
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// combination read
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assign DataOutA = Registers[RaddrA];
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assign DataOutB = Registers[RaddrB];
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// sequential (clocked) writes
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always_ff @ (posedge Clk) begin
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if (Reset) begin // reset all registers to 0 when reset
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for(int i=0; i<2**D; i++) begin
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Registers[i] <= 'h0;
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end
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end
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else if (start) begin
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Registers[Waddr] <= DataIn;
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end
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else if (WriteEn) begin
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Registers[Waddr] <= DataIn;
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end
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end
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endmodule
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