31 lines
625 B
Systemverilog
31 lines
625 B
Systemverilog
// Module Name: Flags
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// Project Name: CSE141L
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// Description: flag registers
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module Flags (
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input logic Clk, Reset, WriteEn, start,
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input logic Zero_in, Done_in,
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output logic Zero_out, Done_out
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);
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logic Zero, Done;
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assign Zero_out = Zero;
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assign Done_out = Done;
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always_ff @(posedge Clk) begin
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if(Reset) begin
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Zero <= 'b0;
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Done <= 'b1; // default Done to halt machine
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end
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else if (start) begin
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Zero <= Zero_in;
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Done <= 'b0;
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end
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else if (WriteEn) begin
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Zero <= Zero_in;
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Done <= Done_in;
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end
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end
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endmodule |