fix file headers

RTL/Ctrl.sv

@@ -1,4 +1,4 @@
-// Module Name: ALU
+// Module Name: Ctrl
 // Project Name: CSE141L
 // control decoder (combinational, not clocked)
 

RTL/DataMem.sv

@@ -1,4 +1,4 @@
-// Module Name: ALU
+// Module Name: DataMem
 // Project Name: CSE141L
 // control decoder (combinational, not clocked)
 

RTL/Definitions.sv

@@ -1,4 +1,4 @@
-// Module Name: ALU
+// Module Name: Definitions
 // Project Name: CSE141L
 // Description: contains enumerated ALU operations
 

RTL/InstFetch.sv

@@ -1,4 +1,4 @@
-// Module Name: ALU
+// Module Name: InstFetch
 // Project Name: CSE141L
 // Description: instruction fetch (pgm ctr) for processor
 

RTL/InstROM.sv

@@ -1,56 +1,18 @@
-// Create Date:    15:50:22 10/02/2019 
+// Module Name: InstFetch
-// Design Name: 
+// Project Name: CSE141L
-// Module Name:    InstROM 
+// Description: instruction ROM module for use with InstFetch
-// Project Name:   CSE141L
-// Tool versions: 
-// Description: Verilog module -- instruction ROM template	
-//	 preprogrammed with instruction values (see case statement)
-//
-// Revision: 2021.08.08
-//
-// A = program counter width
-// W = machine code width -- do not change for CSE141L
-module InstROM #(parameter A=10, W=9) (
-  input       [A-1:0] InstAddress,
-  output logic[W-1:0] InstOut);
-	 
-// (usually recommended) expression
-//   need $readmemh or $readmemb to initialize all of the elements
-// This version will work best with assemblers, but you can try the alternative starting line 33
-// This version is also by far the easiest if you have a long program scrip.  
-// declare 2-dimensional array, W bits wide, 2**A words deep
-  logic[W-1:0] inst_rom[2**A];
-  always_comb InstOut = inst_rom[InstAddress];
- 
-  initial begin		                  // load from external text file
-  	$readmemb("machine_code.txt",inst_rom);
-  end 
-  
-// Sample instruction format: 
-//   {3bit opcode, 3bit rs or rt, 3bit rt, immediate, or branch target}
-//   then use LUT to map 3 bits to 10 for branch target, 8 for immediate	 
 
-/* alternative to code shown below, which may be simpler -- either is fine
+module InstROM #(parameter A=10, W=9) (
-  always_comb begin 
+	input logic [A-1:0] InstAddress,
-	InstOut = 'b0000000000;        // default
+	output logic[W-1:0] InstOut
-	case (InstAddress)
+);
-//opcode = 0 lhw, rs = 0, rt = 1
+	// declare 2-dimensional array, W bits wide, 2**A words deep
-      0 : InstOut = 'b0000000001;  // load from address at reg 0 to reg 1  
+	logic[W-1:0] inst_rom[2**A];
-// opcode = 1 addi, rs/rt = 1, immediate = 1
+	assign InstOut = inst_rom[InstAddress];
-     
+ 
-      1 : InstOut = 'b0001001001;  // addi reg 1 and 1
+	// use readmemb to read ascii 0 and 1 representation of binary values from text file
-		
+	initial begin
-// opcode = 2 shw, rs = 0, rt = 1
+		$readmemb("machine_code.txt",inst_rom);
-      2 : InstOut = 'b0010000001;  // sw reg 1 to address in reg 0
+	end
-		
-// opcode = 3 beqz, rs = 1, target = 1
-      3 : InstOut = 'b0011001001;  // beqz reg1 to absolute address 1
-		
-// opcode = 15 halt
-      4 : InstOut = '1;  // equiv to 10'b1111111111 or 'b1111111111    halt
-// (default case already covered by opening statement)
-    endcase
-  end
-*/
 
 endmodule

RTL/RegFile.sv

@@ -1,4 +1,4 @@
-// Module Name: ALU
+// Module Name: RegFile
 // Project Name: CSE141L
 // Description: register file
 

RTL/top_level.sv

@@ -1,4 +1,4 @@
-// Module Name: ALU
+// Module Name: top_level
 // Project Name: CSE141L
 // Description: top level RTL for processor