alu/cse141L-project
Archived
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix warning casez had no default

Browse Source
This commit is contained in:
Arthur Lu 2022-08-19 21:16:03 -07:00
parent cba9ede657
commit c7b5b8b63c
1 changed files with 25 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
RTL/Ctrl.sv
View File

@ -50,93 +50,96 @@ module Ctrl #(
BranchNZ = 'b0; BranchNZ = 'b0;
BranchAlways = 'b0; BranchAlways = 'b0;
write_mem = 'b0; write_mem = 'b0;
casez(Instruction) casez(Instruction[8:3])
'b1_????_????: begin // LDI 'b1_????_?: begin // LDI
ALU_A = I_Immediate; ALU_A = I_Immediate;
end end
'b0_0000_????: begin // PUT 'b0_0000_?: begin // PUT
Waddr = A_operand; Waddr = A_operand;
end end
'b0_0001_????: begin // GET 'b0_0001_?: begin // GET
RaddrA = A_operand; RaddrA = A_operand;
end end
'b0_0010_0???: begin // LDW 'b0_0010_0: begin // LDW
RaddrA = S_operand; RaddrA = S_operand;
RegInput = mem_out; RegInput = mem_out;
end end
'b0_0010_1???: begin // STW 'b0_0010_1: begin // STW
RaddrA = S_operand; RaddrA = S_operand;
RegWrite = 'b0; RegWrite = 'b0;
write_mem = 'b1; write_mem = 'b1;
end end
'b0_0011_0???: begin // N?T 'b0_0011_0: begin // N?T
if(S_operand == 'd8 || S_operand == 'd9 || S_operand == 'd10) ALU_OP = DEC; if(S_operand == 'd8 || S_operand == 'd9 || S_operand == 'd10) ALU_OP = DEC;
else if (S_operand == 'd11 || S_operand == 'd12 || S_operand == 'd13) ALU_OP = INC; else if (S_operand == 'd11 || S_operand == 'd12 || S_operand == 'd13) ALU_OP = INC;
else ALU_OP = NOP; else ALU_OP = NOP;
RaddrA = S_operand; RaddrA = S_operand;
Waddr = S_operand; Waddr = S_operand;
end end
'b0_0011_1???: begin //CLB 'b0_0011_1: begin //CLB
ALU_OP = CLB; ALU_OP = CLB;
RaddrA = G_operand; RaddrA = G_operand;
Waddr = G_operand; Waddr = G_operand;
end end
'b0_0100_????: begin // ADD 'b0_0100_?: begin // ADD
ALU_OP = ADD; ALU_OP = ADD;
RaddrB = A_operand; RaddrB = A_operand;
end end
'b0_0101_????: begin // SUB 'b0_0101_?: begin // SUB
ALU_OP = SUB; ALU_OP = SUB;
RaddrB = A_operand; RaddrB = A_operand;
end end
'b0_0110_????: begin // ORR 'b0_0110_?: begin // ORR
ALU_OP = ORR; ALU_OP = ORR;
RaddrB = A_operand; RaddrB = A_operand;
end end
'b0_0111_????: begin // AND 'b0_0111_?: begin // AND
ALU_OP = AND; ALU_OP = AND;
RaddrB = A_operand; RaddrB = A_operand;
end end
'b0_1000_0???: begin // LSH 'b0_1000_0: begin // LSH
ALU_OP = LSH; ALU_OP = LSH;
ALU_A = T_Immediate; ALU_A = T_Immediate;
end end
'b0_1000_1???: begin // PTY 'b0_1000_1: begin // PTY
ALU_OP = RXOR_7; ALU_OP = RXOR_7;
RaddrA = G_operand; RaddrA = G_operand;
end end
'b0_1001_????: begin // CHK 'b0_1001_?: begin // CHK
ALU_OP = RXOR_8; ALU_OP = RXOR_8;
RaddrA = A_operand; RaddrA = A_operand;
end end
'b0_1010_????: begin // XOR 'b0_1010_?: begin // XOR
ALU_OP = XOR; ALU_OP = XOR;
RaddrB = A_operand; RaddrB = A_operand;
end end
'b0_1011_????: begin // DNE 'b0_1011_?: begin // DNE
Done_in = 'b1; Done_in = 'b1;
end end
'b0_1110_0???: begin // JNZ 'b0_1110_0: begin // JNZ
RegWrite = 'b0; RegWrite = 'b0;
RaddrA = G_operand; RaddrA = G_operand;
BranchNZ = 'b1; BranchNZ = 'b1;
end end
'b0_1110_1???: begin // JEZ 'b0_1110_1: begin // JEZ
RegWrite = 'b0; RegWrite = 'b0;
RaddrA = G_operand; RaddrA = G_operand;
BranchEZ = 'b1; BranchEZ = 'b1;
end end
'b0_1111_0???: begin // JMP 'b0_1111_0: begin // JMP
RegWrite = 'b0; RegWrite = 'b0;
RaddrA = G_operand; RaddrA = G_operand;
BranchAlways = 'b1; BranchAlways = 'b1;
end end
'b0_1111_1???: begin // JAL 'b0_1111_1: begin // JAL
RaddrA = G_operand; RaddrA = G_operand;
Waddr = 'd14; // write to link register specifically Waddr = 'd14; // write to link register specifically
RegInput = ProgCtr_p1; // write the value pc+4 RegInput = ProgCtr_p1[7:0]; // write the value pc+4
BranchAlways = 'b1; BranchAlways = 'b1;
end end
default: begin
RegWrite = 'b0;
end
endcase endcase
end end