diff --git a/RTL/Ctrl.sv b/RTL/Ctrl.sv
index 8c84a71..ad24255 100644
--- a/RTL/Ctrl.sv
+++ b/RTL/Ctrl.sv
@@ -9,11 +9,11 @@ module Ctrl #(
 	parameter T = 10
 ) (
 	input logic [8:0] Instruction,
-	input logic [W-1:0] ALU_Out, // control ALU operation
+	input logic [W-1:0] ALU_Out,
 	input logic [W-1:0] RegOutA, RegOutB, // select from register inputs or immediate inputs
 	input logic [T-1:0] ProgCtr_p4,
 	input logic [W-1:0] mem_out,
-	output op_mne ALU_OP,
+	output op_mne ALU_OP, // control ALU operation
 	output logic [W-1:0] ALU_A, ALU_B,
 	output logic RegWrite, Done_in,
 	output logic [3:0] RaddrA, RaddrB, Waddr, RegInput,
diff --git a/RTL/InstFetch.sv b/RTL/InstFetch.sv
index 1737b50..581f36d 100644
--- a/RTL/InstFetch.sv
+++ b/RTL/InstFetch.sv
@@ -5,8 +5,9 @@
 module InstFetch #(parameter T=10, parameter W=8)(	  // T is PC address size, W is the jump target pointer width, which is less
 	input logic Clk, Reset, // clock, reset
 	input logic BranchEZ, BranchNZ, BranchAlways, Zero, // branch control signals zero from alu signals; brnahc signals will be one hot encoding
-	input logic done, // Done flag to indicate if the PC should increment at all
+	input logic Done, // Done flag to indicate if the PC should increment at all
 	input logic [W-1:0] Target, // jump target pointer
+	output logic [T-1:0] ProgCtr,
 	output logic [T-1:0] ProgCtr_p4 // value of pc+4 for use in JAL instruction itself
 );
 
@@ -17,7 +18,7 @@ module InstFetch #(parameter T=10, parameter W=8)(	  // T is PC address size, W
 		else if (BranchAlways) PC <= Target; // if unconditional branch, assign PC to target
 		else if (BranchEZ && Zero) PC <= Target; // if branch on zero and zero is true, then assign PC to target
 		else if (BranchNZ && !Zero) PC <= Target; // if branch on non zero and zero is false, then assign PC to parget
-		else if (!done) PC <= PC + 'b1; // if not a branch but CPU is not done, then 
+		else if (!Done) PC <= PC + 'b1; // if not a branch but CPU is not done, then 
 		else PC <= PC;
 	end
 
diff --git a/RTL/top_level.sv b/RTL/top_level.sv
index 296c587..3cca9da 100644
--- a/RTL/top_level.sv
+++ b/RTL/top_level.sv
@@ -1,35 +1,87 @@
-// skeletal starter code top level of your DUT
+// Module Name: ALU
+// Project Name: CSE141L
+// Description: top level RTL for processor
+
+import Definitions::*;
+
 module top_level(
-  input clk, init, req,
-  output logic ack);
+	input clk, init, req,
+	output logic ack
+);
 
-  logic mem_wen;
-  logic[7:0]  mem_addr,
-              mem_in,
-			  mem_out;
-  logic[11:0] pctr;		  // temporary program counter
+	parameter T=10;
+	parameter W=8;
 
-// populate with program counter, instruction ROM, reg_file (if used),
-//  accumulator (if used), 
+	logic [8:0] Instruction;
+	logic [W-1:0] ALU_Out; 
+	logic [W-1:0] RegOutA, RegOutB; // select from register inputs or immediate inputs
+	logic [T-1:0] ProgCtr_p4;
+	logic [W-1:0] mem_out;
+	op_mne ALU_OP; // control ALU operation
+	logic [W-1:0] ALU_A, ALU_B;
+	logic RegWrite, Done_in;
+	logic [3:0] RaddrA, RaddrB, Waddr, RegInput;
+	logic BranchEZ, BranchNZ, BranchAlways;
+	logic write_mem;
+	logic Zero_in, Zero_out;
+	logic Done_out;
+	logic [T-1:0] ProgCtr;
 
-DataMem DM(.Clk         (clk), 
-           .Reset       (init), 
-           .WriteEn     (mem_wen), 
-           .DataAddress (mem_addr), 
-           .DataIn      (mem_in), 
-           .DataOut     (mem_out));
+	Ctrl #() c (.*);
 
+	ALU #() a (
+		.A(ALU_A),
+		.B(ALU_B),
+		.ALU_OP(ALU_OP),
+		.Out(ALU_Out),
+		.Zero(Zero_in)
+	);
 
-// temporary circuit to provide ack (done) flag to test bench
-//   remove or greatly increase the match value once you get a 
-//   proper ack 
-always @(posedge clk) 
-  if(init || req) 
-    pctr <= 'h0;
-  else  
-	pctr <= pctr+'h1;
+	InstFetch #() pc (
+		.Clk(clk),
+		.Reset(init),
+		.BranchEZ(BranchEZ),
+		.BranchNZ(BranchNZ),
+		.BranchAlways(BranchAlways),
+		.Zero(Zero_out),
+		.Done(Done_out),
+		.Target(ALU_A),
+		.ProgCtr(ProgCtr),
+		.ProgCtr_p4(ProgCtr_p4)
+	);
 
-assign ack = pctr=='h256;  // pctr needed to trigger ack (arbitary time)
+	RegFile #() r (
+		.Clk(clk),
+		.Reset(init),
+		.WriteEn(RegWrite),
+		.RaddrA(RaddrA),
+		.RaddrB(RaddrB),
+		.Waddr(Waddr),
+		.DataIn(RegInput),
+		.Zero_in(Zero_in),
+		.Done_in(Done_in),
+		.start(req),
+		.DataOutA(RegOutA),
+		.DataOutB(RegOutB),
+		.Zero_out(Zero_out),
+		.Done_out(Done_out)
+	);
+
+	DataMem #() d (
+		.Clk(clk),
+		.Reset(init),
+		.WriteEn(write_mem),
+		.DataAddress(ALU_Out),
+		.DataIn(RegOutB),
+		.DataOut(mem_out)
+	);
+
+	InstROM #() i (
+		.InstAddress(ProgCtr),
+		.InstOut(Instruction)
+	);
+
+	assign ack = Done_out;
 
 endmodule