diff --git a/RTL/Ctrl.sv b/RTL/Ctrl.sv
index e5993cb..68ada56 100644
--- a/RTL/Ctrl.sv
+++ b/RTL/Ctrl.sv
@@ -25,14 +25,10 @@ module Ctrl #(
 	logic [7:0] I_Immediate;
 	logic [7:0] T_Immediate;
 	logic [3:0] A_operand;
-	logic [3:0] S_operand;
-	logic [3:0] G_operand;
 
 	assign I_Immediate = Instruction[7:0];
 	assign T_Immediate = Instruction[2:0];
 	assign A_operand = Instruction[3:0];
-	assign S_operand = {1'b1, Instruction[2:0]};
-	assign G_operand = {1'b0, Instruction[2:0]};
 
 	always_comb begin
 		// default values for an invalid NOP instruction, proper NOP instruction encoded as a LSH by 0
@@ -49,90 +45,87 @@ module Ctrl #(
 		BranchNZ = 'b0;
 		BranchAlways = 'b0;
 		write_mem = 'b0;
-		casez(Instruction[8:4])
-			'b1_????: begin // LDI
-				ALU_A = I_Immediate;
-			end
-			'b0_0000: begin // PUT
+		if(Instruction[8]) begin
+			ALU_A = I_Immediate;
+		end
+		else case(Instruction[7:4])
+			'b0000: begin // PUT
 				Waddr = A_operand;
 			end
-			'b0_0001: begin // GET
+			'b0001: begin // GET
 				RaddrA = A_operand;
 			end
-			'b0_0010: begin // LDW
-				RaddrA = S_operand;
+			'b0010: begin // LDW
+				RaddrA = A_operand;
 				RegInput = mem_out;
 			end
-			'b0_0011: begin // STW
-				RaddrA = S_operand;
+			'b0011: begin // STW
+				RaddrA = A_operand;
 				RegWrite = 'b0;
 				write_mem = 'b1;
 			end
-			'b0_0100: begin // NXT
-				if(S_operand == 'd8 || S_operand == 'd9 || S_operand == 'd10) begin
+			'b0100: begin // NXT
+				if(A_operand == 'd8 || A_operand == 'd9 || A_operand == 'd10) begin
 					ALU_OP = SUB;
 					ALU_B = 'b1;
 				end
-				else if (S_operand == 'd11 || S_operand == 'd12 || S_operand == 'd13) begin
+				else if (A_operand == 'd11 || A_operand == 'd12 || A_operand == 'd13) begin
 					ALU_OP = ADD;
 					ALU_B = 'b1;
 				end
 				else ALU_OP = NOP;
-				RaddrA = S_operand;
-				Waddr = S_operand;
+				RaddrA = A_operand;
+				Waddr = A_operand;
 			end
-			'b0_0101: begin //CLB
+			'b0101: begin //CLB
 				ALU_OP = CLB;
-				RaddrA = G_operand;
-				Waddr = G_operand;
+				RaddrA = A_operand;
+				Waddr = A_operand;
 			end
-			'b0_0110: begin // ADD
+			'b0110: begin // ADD
 				ALU_OP = ADD;
 				RaddrA = A_operand;
 			end
-			'b0_0111: begin // AND
+			'b0111: begin // AND
 				ALU_OP = AND;
 				RaddrA = A_operand;
 			end
-			'b0_1000: begin // LSH
+			'b1000: begin // LSH
 				ALU_OP = LSH;
 				ALU_A = T_Immediate;
 			end
-			'b0_1001: begin // RXR
+			'b1001: begin // RXR
 				ALU_OP = RXOR;
 				RaddrA = A_operand;
 			end
-			'b0_1010: begin // XOR
+			'b1010: begin // XOR
 				ALU_OP = XOR;
 				RaddrA = A_operand;
 			end
-			'b0_1011: begin // DNE
+			'b1011: begin // DNE
 				Done_in = 'b1;
 			end
-			'b0_1100: begin // JNZ
+			'b1100: begin // JNZ
 				RegWrite = 'b0;
-				RaddrA = G_operand;
+				RaddrA = A_operand;
 				BranchNZ = 'b1;
 			end
-			'b0_1101: begin // JEZ
+			'b1101: begin // JEZ
 				RegWrite = 'b0;
-				RaddrA = G_operand;
+				RaddrA = A_operand;
 				BranchEZ = 'b1;
 			end
-			'b0_1110: begin // JMP
+			'b1110: begin // JMP
 				RegWrite = 'b0;
-				RaddrA = G_operand;
+				RaddrA = A_operand;
 				BranchAlways = 'b1;
 			end
-			'b0_1111: begin // JAL
-				RaddrA = G_operand;
+			'b1111: begin // JAL
+				RaddrA = A_operand;
 				Waddr = 'd14; // write to link register specifically
 				RegInput = ProgCtr_p1[7:0]; // write the value pc+4
 				BranchAlways = 'b1;
 			end
-			default: begin
-				RegWrite = 'b0;
-			end
 		endcase
 	end
 
diff --git a/firmware/assembler.py b/firmware/assembler.py
index e7a4442..ab065e8 100644
--- a/firmware/assembler.py
+++ b/firmware/assembler.py
@@ -49,9 +49,9 @@ op_codes = {
 	'LDI': 0b1_0000_0000,
 	'PUT': 0b0_0000_0000,
 	'GET': 0b0_0001_0000,
-	'LDW': 0b0_0010_0000,
-	'STW': 0b0_0011_0000,
-	'NXT': 0b0_0100_0000,
+	'LDW': 0b0_0010_1000,
+	'STW': 0b0_0011_1000,
+	'NXT': 0b0_0100_1000,
 	'CLB': 0b0_0101_0000,
 	'ADD': 0b0_0110_0000,
 	'AND': 0b0_0111_0000,