diff --git a/RTL/Flags.sv b/RTL/Flags.sv
new file mode 100644
index 0000000..6330f5e
--- /dev/null
+++ b/RTL/Flags.sv
@@ -0,0 +1,31 @@
+// Module Name: Flags
+// Project Name: CSE141L
+// Description: flag registers
+
+module Flags (
+    input logic Clk, Reset, WriteEn, start,
+    input logic Zero_in, Done_in,
+    output logic Zero_out, Done_out
+);
+
+    logic Zero, Done;
+
+    assign Zero_out = Zero;
+	assign Done_out = Done;
+
+    always_ff @(posedge Clk) begin
+        if(Reset) begin
+            Zero <= 'b0;
+			Done <= 'b1; // default Done to halt machine
+        end
+        else if (start) begin
+			Zero <= Zero_in;
+			Done <= 'b0;
+		end
+		else if (WriteEn) begin
+			Zero <= Zero_in;
+			Done <= Done_in;
+		end
+    end
+
+endmodule
\ No newline at end of file
diff --git a/RTL/RegFile.sv b/RTL/RegFile.sv
index 275bfaf..a4f55fb 100644
--- a/RTL/RegFile.sv
+++ b/RTL/RegFile.sv
@@ -3,23 +3,18 @@
 // Description: register file
 
 module RegFile #(parameter W=8, D=4)(		 // W = data path width (leave at 8); D = address pointer width
-	input Clk, Reset, WriteEn,
-	input [D-1:0] RaddrA, RaddrB, Waddr, // read anad write address pointers
-	input [W-1:0] DataIn, // data to be written
-	input logic Zero_in, Done_in, // since flags are stored in register file, need this as an input
+	input logic Clk, Reset, WriteEn,
+	input logic [D-1:0] RaddrA, RaddrB, Waddr, // read anad write address pointers
+	input logic [W-1:0] DataIn, // data to be written
 	input logic start, // start signal from testbench
-	output logic [W-1:0] DataOutA, DataOutB, // data to read out
-	output logic Zero_out, Done_out // output of zero and done flags
+	output logic [W-1:0] DataOutA, DataOutB // data to read out
 );
 
 	logic [W-1:0] Registers[2**D]; // 2^D registers of with W
-	logic Zero, Done;
 
 	// combination read
 	assign DataOutA = Registers[RaddrA];
 	assign DataOutB = Registers[RaddrB];
-	assign Zero_out = Zero;
-	assign Done_out = Done;
 
 	// sequential (clocked) writes 
 	always_ff @ (posedge Clk) begin
@@ -27,18 +22,12 @@ module RegFile #(parameter W=8, D=4)(		 // W = data path width (leave at 8); D =
 			for(int i=0; i<2**D; i++) begin
 				Registers[i] <= 'h0;
 			end
-			Zero <= 'b0;
-			Done <= 'b1; // default Done to halt machine
 		end
 		else if (start) begin
 			Registers[Waddr] <= DataIn;
-			Zero <= Zero_in;
-			Done <= 'b0;
 		end
 		else if (WriteEn) begin
 			Registers[Waddr] <= DataIn;
-			Zero <= Zero_in;
-			Done <= Done_in;
 		end
 	end
 
diff --git a/RTL/top_level.sv b/RTL/top_level.sv
index d35e926..0a6789a 100644
--- a/RTL/top_level.sv
+++ b/RTL/top_level.sv
@@ -59,13 +59,9 @@ module top_level(
 		.RaddrB(RaddrB),
 		.Waddr(Waddr),
 		.DataIn(RegInput),
-		.Zero_in(Zero_in),
-		.Done_in(Done_in),
 		.start(req),
 		.DataOutA(RegOutA),
-		.DataOutB(RegOutB),
-		.Zero_out(Zero_out),
-		.Done_out(Done_out)
+		.DataOutB(RegOutB)
 	);
 
 	DataMem DM (
@@ -81,6 +77,17 @@ module top_level(
 		.InstOut(Instruction)
 	);
 
+	Flags f (
+		.Clk(clk),
+		.Reset(init),
+		.WriteEn(RegWrite),
+		.start(req),
+		.Zero_in(Zero_in),
+		.Zero_out(Zero_out),
+		.Done_in(Done_in),
+		.Done_out(Done_out)
+	);
+
 	assign ack = Done_out;
 
 endmodule