diff --git a/RTL/ALU.sv b/RTL/ALU.sv
index 4d62317..b4f05d9 100644
--- a/RTL/ALU.sv
+++ b/RTL/ALU.sv
@@ -27,4 +27,4 @@ module ALU #(parameter W=8)(
 		endcase
 		Zero = Out == 0;
 	end
-endmodule
+endmodule
\ No newline at end of file
diff --git a/RTL/Ctrl.sv b/RTL/Ctrl.sv
index 533f340..792734a 100644
--- a/RTL/Ctrl.sv
+++ b/RTL/Ctrl.sv
@@ -88,19 +88,19 @@ module Ctrl #(
 			end
 			'b0_0100_?: begin // ADD
 				ALU_OP = ADD;
-				RaddrB = A_operand;
+				RaddrA = A_operand;
 			end
 			'b0_0101_?: begin // SUB
 				ALU_OP = SUB;
-				RaddrB = A_operand;
+				RaddrA = A_operand;
 			end
 			'b0_0110_?: begin // ORR
 				ALU_OP = ORR;
-				RaddrB = A_operand;
+				RaddrA = A_operand;
 			end
 			'b0_0111_?: begin // AND
 				ALU_OP = AND;
-				RaddrB = A_operand;
+				RaddrA = A_operand;
 			end
 			'b0_1000_0: begin // LSH
 				ALU_OP = LSH;
@@ -116,7 +116,7 @@ module Ctrl #(
 			end
 			'b0_1010_?: begin // XOR
 				ALU_OP = XOR;
-				RaddrB = A_operand;
+				RaddrA = A_operand;
 			end
 			'b0_1011_?: begin // DNE
 				Done_in = 'b1;