remove ORR instruction
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@ -35,7 +35,6 @@ module ALU #(parameter W=8)(
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CIN = 'b1;
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Out = AdderResult[W-1:0];
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end
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ORR: Out = A | B; // bitwise OR between A and B
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AND: Out = A & B; // bitwise AND between A and B
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LSH: Out = B << A; // shift B by A bits (limitation of control)
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RXOR_7: Out = ^(A[6:0]); // perform reduction XOR of lower 7 bits of A
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@ -90,10 +90,6 @@ module Ctrl #(
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ALU_OP = ADD;
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RaddrA = A_operand;
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end
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'b0_0110_?: begin // ORR
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ALU_OP = ORR;
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RaddrA = A_operand;
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end
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'b0_0111_?: begin // AND
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ALU_OP = AND;
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RaddrA = A_operand;
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@ -35,7 +35,7 @@ op_type = {
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'CLB': 'G',
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'ADD': 'A',
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#'SUB': 'A',
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'ORR': 'A',
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#'ORR': 'A',
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'AND': 'A',
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'LSH': 'T',
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'PTY': 'G',
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@ -58,7 +58,7 @@ op_codes = {
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'CLB': 0b0_0011_1000,
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'ADD': 0b0_0100_0000,
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#'SUB': 0b0_0101_0000,
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'ORR': 0b0_0110_0000,
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#'ORR': 0b0_0110_0000,
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'AND': 0b0_0111_0000,
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'LSH': 0b0_1000_0000,
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'PTY': 0b0_1000_1000,
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@ -56,7 +56,7 @@ lfsr_routine: GET r7 // get previous state
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PUT r1 // store feedback bit to r1 temporarily
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GET r7 // get previous state again
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LSH #d1 // left shift previous state by 1
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ORR r1 // or with parity bit to get next state
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XOR r1 // or with parity bit to get next state
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PUT r7 // put next state to r7
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GET r14 // load link register
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JMP r0 // return to function call address
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@ -98,7 +98,7 @@ lfsr_routine: GET r7 // get previous state
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PUT r1 // store feedback bit to r1 temporarily
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GET r7 // get previous state again
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LSH #d1 // left shift previous state by 1
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ORR r1 // or with parity bit to get next state
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XOR r1 // or with parity bit to get next state
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PUT r7 // put next state to r7
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GET r14 // load link register
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JMP r0 // return to function call address
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@ -139,7 +139,7 @@ lfsr_routine: GET r7 // get previous state
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PUT r1 // store feedback bit to r1 temporarily
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GET r7 // get previous state again
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LSH #d1 // left shift previous state by 1
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ORR r1 // or with parity bit to get next state
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XOR r1 // or with parity bit to get next state
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PUT r7 // put next state to r7
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GET r14 // load link register
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JMP r0 // return to function call address
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