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fixed bugs in synthesis

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This commit is contained in:
Arthur Lu 2022-08-13 18:54:10 -07:00
parent 3c77111bfd
commit 0dbd5dbbea
3 changed files with 29 additions and 29 deletions
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4
RTL/Ctrl.sv
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@ -30,8 +30,8 @@ module Ctrl #(
assign I_Immediate = Instruction[7:0];
assign T_Immediate = Instruction[2:0];
assign A_operand = Instruction[3:0];
assign S_operand = {'b1, Instruction[2:0]};
assign G_operand = {'b0, Instruction[2:0]};
assign S_operand = {1'b1, Instruction[2:0]};
assign G_operand = {1'b0, Instruction[2:0]};
assign ALU_B = RegOutB;

12
RTL/top_level.sv
View File

@ -27,9 +27,9 @@ module top_level(
logic Done_out;
logic [T-1:0] ProgCtr;
Ctrl #() control (.*);
Ctrl control (.*);
ALU #() alu (
ALU alu (
.A(ALU_A),
.B(ALU_B),
.ALU_OP(ALU_OP),
@ -37,7 +37,7 @@ module top_level(
.Zero(Zero_in)
);
InstFetch #() pc (
InstFetch pc (
.Clk(clk),
.Reset(init),
.BranchEZ(BranchEZ),
@ -50,7 +50,7 @@ module top_level(
.ProgCtr_p4(ProgCtr_p4)
);
RegFile #() regfile (
RegFile regfile (
.Clk(clk),
.Reset(init),
.WriteEn(RegWrite),
@ -67,7 +67,7 @@ module top_level(
.Done_out(Done_out)
);
DataMem #() datamem (
DataMem datamem (
.Clk(clk),
.Reset(init),
.WriteEn(write_mem),
@ -76,7 +76,7 @@ module top_level(
.DataOut(mem_out)
);
InstROM #() rom (
InstROM rom (
.InstAddress(ProgCtr),
.InstOut(Instruction)
);