fixed bugs in synthesis

RTL/Ctrl.sv

@@ -30,8 +30,8 @@ module Ctrl #(
 	assign I_Immediate = Instruction[7:0];
 	assign T_Immediate = Instruction[2:0];
 	assign A_operand = Instruction[3:0];
-	assign S_operand = {'b1, Instruction[2:0]};
+	assign S_operand = {1'b1, Instruction[2:0]};
-	assign G_operand = {'b0, Instruction[2:0]};
+	assign G_operand = {1'b0, Instruction[2:0]};
 
 	assign ALU_B = RegOutB;
 

RTL/InstROM.sv

@@ -7,30 +7,30 @@
 //	 preprogrammed with instruction values (see case statement)
 //
 // Revision: 2021.08.08
-//
+//
-// A = program counter width
+// A = program counter width
 // W = machine code width -- do not change for CSE141L
 module InstROM #(parameter A=12, W=9) (
   input       [A-1:0] InstAddress,
   output logic[W-1:0] InstOut);
 	 
-// (usually recommended) expression
+// (usually recommended) expression
-//   need $readmemh or $readmemb to initialize all of the elements
+//   need $readmemh or $readmemb to initialize all of the elements
-// This version will work best with assemblers, but you can try the alternative starting line 33
+// This version will work best with assemblers, but you can try the alternative starting line 33
-// This version is also by far the easiest if you have a long program scrip.  
+// This version is also by far the easiest if you have a long program scrip.  
-// declare 2-dimensional array, W bits wide, 2**A words deep
+// declare 2-dimensional array, W bits wide, 2**A words deep
-  logic[W-1:0] inst_rom[2**A];
+  logic[W-1:0] inst_rom[2**A];
-  always_comb InstOut = inst_rom[InstAddress];
+  always_comb InstOut = inst_rom[InstAddress];
- 
+ 
-  initial begin		                  // load from external text file
+  initial begin		                  // load from external text file
-  	$readmemb("machine_code.txt",inst_rom);
+  	$readmemb("machine_code.txt",inst_rom);
-  end 
+  end 
   
-// Sample instruction format: 
+// Sample instruction format: 
 //   {3bit opcode, 3bit rs or rt, 3bit rt, immediate, or branch target}
 //   then use LUT to map 3 bits to 10 for branch target, 8 for immediate	 
-
+
-/* alternative to code shown below, which may be simpler -- either is fine
+/* alternative to code shown below, which may be simpler -- either is fine
   always_comb begin 
 	InstOut = 'b0000000000;        // default
 	case (InstAddress)
@@ -48,9 +48,9 @@ module InstROM #(parameter A=12, W=9) (
 		
 // opcode = 15 halt
       4 : InstOut = '1;  // equiv to 10'b1111111111 or 'b1111111111    halt
-// (default case already covered by opening statement)
+// (default case already covered by opening statement)
-    endcase
+    endcase
-  end
+  end
-*/
+*/
-
+
 endmodule

RTL/top_level.sv

@@ -27,9 +27,9 @@ module top_level(
 	logic Done_out;
 	logic [T-1:0] ProgCtr;
 
-	Ctrl #() control (.*);
+	Ctrl control (.*);
 
-	ALU #() alu (
+	ALU alu (
 		.A(ALU_A),
 		.B(ALU_B),
 		.ALU_OP(ALU_OP),
@@ -37,7 +37,7 @@ module top_level(
 		.Zero(Zero_in)
 	);
 
-	InstFetch #() pc (
+	InstFetch pc (
 		.Clk(clk),
 		.Reset(init),
 		.BranchEZ(BranchEZ),
@@ -50,7 +50,7 @@ module top_level(
 		.ProgCtr_p4(ProgCtr_p4)
 	);
 
-	RegFile #() regfile (
+	RegFile regfile (
 		.Clk(clk),
 		.Reset(init),
 		.WriteEn(RegWrite),
@@ -67,7 +67,7 @@ module top_level(
 		.Done_out(Done_out)
 	);
 
-	DataMem #() datamem (
+	DataMem datamem (
 		.Clk(clk),
 		.Reset(init),
 		.WriteEn(write_mem),
@@ -76,7 +76,7 @@ module top_level(
 		.DataOut(mem_out)
 	);
 
-	InstROM #() rom (
+	InstROM rom (
 		.InstAddress(ProgCtr),
 		.InstOut(Instruction)
 	);